The objective of this research is to analyze and improve linearity of envelope elimination and restoration (EER) radio frequency (RF) power amplifiers. Envelope elimination and restoration was compared to other efficiency enhancement techniques and determined to likely be the most suitable solution for implementation of multimode, multiband portable RF transmitters. Distortion, stemming from dynamic power-supply modulation of RF transistors in EER RF power amplifiers was identified as one of the key challenges to the development of commercially viable EER transmitters. This dissertation presents a study of phase distortion in RF power amplifiers (PAs) with emphasis on identification of the origins of phase distortion in EER RF power amplifiers. Circuit-level techniques for distortion mitigation are also presented. Memory effects in conventional power amplifiers are investigated through the accurate measurement and analysis of phase asymmetry of out-of-band distortion components. Novel physically-based power amplifier model is developed for attributing measured memory effects to their physical origin. The amount of linearity correction, obtained through pre-distortion for a particular RF power amplifier, is then correlated to the behavior of the memory effects in the corresponding PA. Heterojunction field-effect transistor and heterojunction bipolar transistor amplifiers are used for investigation of voltage-dependent phase distortion in handset EER RF PAs. The distortion is found to stem from vector addition of signals, generated in nonlinear circuit elements of the PA. Specifically, nonlinear base-collector capacitance and downconversion of distortion components from second harmonic frequency are found to be the dominant sources of phase distortion. Shorting of second harmonic is proposed as a way to reduce the distortion contribution of the downconverted signal. Phase distortion is reduced by 50%, however a slight degradation in the amplitude distortion is observed. Push-pull architecture is proposed for EER RF power amplifiers to cancel distortion components, generated in the nonlinear base-collector capacitance. Push-pull implementation enables a 67% reduction in phase distortion, accompanied by a 1-2 dB reduction in amplitude distortion in EER RF power amplifiers. This work, combined with other studies in the field, will help advance the development of multimode, multiband portable RF transmitters, based on the envelope elimination and restoration architecture.

Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais. / This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.

Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais. / This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.

No / 5th Generation mobile networks (5G) and mobile communications technologies beyond 2020 will need to be energy aware so as to support services that are likely to be intelligent and bandwidth hungry, as well as to support multi-mode operation (LTE, LTE+, HSDPA, 3G among others) in a HetNet environment. This imposes stringent design requirements on the RF transceiver, a key consumer of power in networks today. This chapter will investigate the key RF subsystems forming part of the 5G RF transceiver, where energy efficiency and full radio flexibility are at the forefront of system design. In particular, we target advanced designs on antenna systems, RF power amplifiers and the challenges facing cross-talk in MIMO architectures.

An RF switch in substrate integrated waveguide (SIW) technology for X-band is designed and demonstrated. Design is based on embedding shunt pin diodes of the switch in an evanescent mode waveguide filter. At reverse bias, pin diodes formed a part of filter&#039 / s capacitances. Thus switch also functions as a filter when it is in &ldquo / on&rdquo / state. At forward bias of diodes, capacitances of the filter are short circuited to obtain a good isolation. The same circuit structure is used to design a tunable filter and an RF power limiter which also functions as a filter. Several RF functions usually used in RF frontends (power limiting, filtering, switching) are combined in a single circuit which helps miniaturization of the frontend. The circuit can be produced with standard PCB and chip&amp / wire technology. The circuits developed have comparable performances with microstrip counterparts and they are advantageous to use in microwave systems using SIW as the basic transmission medium and need filtering functionality.

On this thesis work, design and construction of an up to date complete RF excitation system was intended. This excitation system is mainly based on highly efficient switching power generators and proper coupling of the power to the object plasma. This new excitation system design should answer the demands of today&#039 / s progressed CO2 lasers on various power ranges. Though it could be used by a large variety of applications including RF plasma and RF heating, on the first occasion in order to define design considerations, this system is to be exploited by RF excited fast flow and RF excited slab CO2 laser constructions.

Les systèmes de transmission de l’information sans fil connaissent un essor considérable et sont intégrés dans la plupart des systèmes électroniques modernes. De manière plus spécifique, la consommation énergétique de la fonction amplification de puissance RF, qui constitue le cœur de ce travail de recherche, est un enjeu économique et écologique de premier plan. Dans ce sens, ce travail présente une architecture de polarisation de drain dynamique permettant de maintenir un rendement énergétique élevé sur une large dynamique de puissance de sortie. La conception et la réalisation d’un amplificateur de puissance RF large bande, d’un modulateur de polarisation de drain haute fréquence et d’un pilote de grille en technologie GaN sont présentés. L’architecture proposée démontre une amélioration du rendement énergétique global. Une focalisation sur la problématique de couplage non-linéaire entre l’amplificateur de puissance RF et le module d’alimentation agile met en évidence les répercussions de cette méthode sur l’intégrité du signal. Une étroite impulsion de polarisation de grille est appliquée afin d'atténuer l’impact de la polarisation dynamique de drain sur les formes d'onde de l'enveloppe du signal RF amplifié. Une validation expérimentale du démonstrateur proposée est effectuée pour un signal impulsionnel RF multi-niveaux de test. Cette méthode permet de maintenir un facteur de forme de l’enveloppe du signal de sortie RF quasi-rectangulaire sans impact majeur sur les performances globales énergétiques. / Wireless communications are experiencing tremendous growth and are integrated into most modern electronic systems. More precisely, saving energy consumption of RF power amplifier is the core of this thesis work. This work presents a dynamic drain bias architecture used to keep a high efficiency over a large output power range. Design and implementation of a wideband RF power amplifier, a drain supply modulator and a gate driver circuit in GaN technology are presented. The built-in prototype demonstrates an overall efficiency improvement. A specific focus on non-linear interaction between the RF power amplifier and the drain supply modulator highlights the effects of this technique on the output envelope signal shape. A narrow pulse gate bias peaking preceding drain bias voltage variations is applied in order to mitigate drain bias current, voltage overshoot and power droop, thus improving pulse envelope waveforms of the RF output signal. An experimental validation of the proposed demonstrator is performed for a RF pulsed test sequence having different power levels. This way enables to keep rectangular pulse envelope shape at the RF output signal without any major impact on overall efficiency performances.

This diploma thesis is focused on design of high frequency power amplifiers in UHF band, specifically at 435 MHz. Amplifiers are designed in different classes of operation. The thesis deals with the comparison of main parameters in each class of operation, the most important parameter is effeciency. The amplifying part is unipolar transistor which is working in Single-stage mode. The results were simulated in Advanced Design Systems Software.

No description available.

<p>The development of a deuterium-deuterium/ tritium-deuterium (D-D/ D-T) pulsed neutron generator based on the principle of the Plasma Immersion Ion Implantation (PI3) technique is presented, in terms of investigating development of a compact system to generate an ultra short burst of mono-energetic neutrons (of order 1010 per second) during a short period of time (&lt / 20&mu / s) at repetition rates up to 1 kHz. The system will facilitate neutron detection techniques, such as neutron back-scattering, neutron radiography and time-of-flight activation analysis.</p> <p><br /> Aspects addressed in developing the system includes (a) characterizing the neutron spectra generated as a function of the target configuration/ design to ensure a sustained intense neutron flux for long periods of time, (b) the system was also characterised as a function of power supply operating conditions such as voltage, current, gas pressure and plasma density.</p>