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Conselho Nacional de Desenvolvimento Científico e Tecnológico / The power consumption reduction in the fast Fourier transform (FFT) is important because applications in battery-powered embedded systems grows daily. Thus this work focuses on the application of techniques to reduce power in specific projects of FFT algorithms. The goal is to achieve an architectural exploration in the FFT core, the decimation in time butterfly radix-2 and the efficient implementation of arithmetic operators in the internal structure of this butterfly. The techniques applied to the butterfly are aimed at reducing power consumption through architectural exploration and data encryption. Five different butterfly topologies are shown, one of those, proposed in this work uses three real multipliers, and is based on the previous storage of the product of real and imaginary values of the twiddle factors. The advantage of this topology is the possibility of using 4:2 adder compressors, which performs the sum of four operands simultaneously with reduced critical path. These adder compressors have XOR gates in the critical path, is proposed in this paper a new XOR gate circuit, which is based on the use of pass transistors logic. This new XOR gate circuit has been applied to adder compressors 3:2 and 4:2, which are applied to adders blocks of the butterflies. Digital circuits have been developed in hardware description language and some in the electrical schematic level. Results of area, power consumption and cell count in the logic synthesis in 180nm at 100MHz and 20MHz with switching activity analysis for 10,000 random input vectors were obtained for this work. The electrical level simulations in an environment of mixed digital and analog signals were also performed to the evaluation of the compressors with new topology of XOR gate. Analyses show that 3:2 adder compressor has lower power consumption using the new XOR gate circuit. However, the same conclusion was not achieve in relation to the 4:2 adder compressor which has a lower power consumption using the CMOS XOR gate. Butterfly structures evaluated uses a significant amount of arithmetic operators in their internal structures, so was used different design strategies for implementation. Initially was used the arithmetic operators of automatic synthesis tool (Cadence). After, used dedicated arithmetic operators (adder compressors with the new XOR gate circuit, RNS adders and array multipliers). The results show that butterflies have lower power consumption with the use of adder compressors in their internal structures. / A redução no consumo de potência na transformada rápida de Fourier (FFT) é importante pois sua aplicação cresce em sistemas embarcados movidos à bateria. Sendo assim este trabalho tem como foco a aplicação de técnicas de redução de potência para projetos específicos de algoritmos da FFT. O objetivo é realizar uma exploração arquitetural no elemento central de cálculo da FFT, borboleta na base 2 com decimação no tempo, bem como a aplicação de operadores aritméticos eficientes na estrutura interna desta borboleta. As técnicas aplicadas à borboleta têm por objetivo a redução do consumo de potência através de exploração arquitetural e codificação de dados. São apresentadas cinco diferentes topologias de borboleta, sendo uma destas, proposta no âmbito deste trabalho utilizando três multiplicadores reais é baseada no armazenamento prévio do produto dos valores real e imaginário dos coeficientes. A vantagem desta topologia é a possibilidade do uso de somadores compressores 4:2, que realiza a soma simultânea de quatro operandos, com reduzido caminho crítico. Como estes somadores compressores apresentam portas XOR no caminho crítico, é proposta neste trabalho uma nova porta XOR, que é baseada no uso de transistores de passagem. Esta nova porta lógica XOR foi aplicada em somadores compressores 3:2 e 4:2, que são aplicados nos blocos somadores das borboletas. Os circuitos digitais foram desenvolvidos em linguagem de descrição de hardware e alguns em esquemáticos de nível elétrico. Resultados de área, potência e contagem de células na síntese lógica em 180nm a 100MHz e 20MHz com análise de atividade de chaveamento para 10.000 vetores aleatórios de entrada foram obtidos e simulações no nível elétrico em um ambiente de sinais digitais e analógicos misto também foram realizadas para a avaliação dos compressores com a nova topologia de porta XOR. As análises mostram que os somadores compressores 3:2 apresentam menor consumo de potência com o uso da nova porta XOR. Entretanto, o mesmo não se observa em relação ao compressor 4:2 que apresenta um menor consumo de potência utilizando a porta XOR CMOS. Como as estruturas de borboleta avaliadas utilizam uma quantidade significativa de operadores aritméticos nas suas estruturas internas, foram utilizadas diferentes estratégias de projeto para as suas implementações. Inicialmente foram utilizados os operadores aritméticos da ferramenta de síntese automática (Cadence). Após, foram utilizados operadores aritméticos dedicados (somadores compressores com a nova porta XOR, somadores RNS e multiplicadores array). Os resultados mostram que as borboletas apresentam menores consumos de potência com o uso dos somadores compressores em suas estruturas.

Denna rapport täcker arbetsprocessen bakom att skapa en spektrumanalysator. Läsaren kommer att få läsa om den valda metoden men även alternativa metoder. Utöver detta kommer även de teoretiska delarna bakom varje moment att undersökas samt jämföras med potentiella alternativa lösningar. Projektet har utförts på uppdrag av KA Automation. Syftet med projektet var att skapa en basplattform för analys av ljudfrekvenser. Målet med detta var att kunna identifiera ljudegenskaper i form av frekvenserna hos exempelvis servomotorer i vattenpumpar. Tanken var att i ett senare utvecklingsskede kunna identifiera om och när nya frekvenser dykt upp i ljudprofilen vilket i sådana fall kan resultera i att motorn är i behov av service. Basplattformen är uppbyggd med hjälp av C# och ljudbehandlingsbiblioteket NAudio. Från resultatet kan slutsatsen dras att detta program kan analysera ljud och visa de olika frekvensernas styrka och därmed är en lämplig basplattform för vidareutveckling. / This report will cover the work process behind creating a spectrum analyzer. The reader will be able to read about the chosen method but also the alternative methods. Apart from this the theoretical parts behind every moment will also be covered and compared to potential alternative solutions. The project has been carried out on behalf of KA Automation. The purpose of the project was to create a base for analyzing sound frequencies. The goal was to be able to identify sound properties in the form of frequencies in servo motors in for example water pumps. The idea was to be able to in a later development stage be able to identify when new frequencies have entered the audio profile which might result in the motor to be in need of service. The base is created with the help of C# and the sound library NAudio. From the result one can conclude that this program can analyze sound and display the magnitude of its frequency components and is therefore a suitable base for future development.

Cette thèse traite le problème d'intégration hardware optimale de contrôleurs linéaires à taille de mot finie, dédiés aux applications MEMS. Le plus grand défi est d'assurer des performances de contrôle satisfaisantes avec un minimum de ressources logiques. Afin d'y parvenir, deux optimisations distinctes mais complémentaires peuvent être entreprises: en théorie de contrôle et en arithmétique binaire. Seule cette dernière est considérée dans ce travail.Comme cette arithmétique cible des applications MEMS, elle doit faire preuve de vitesse afin de prendre en charge la dynamique rapide des MEMS, à faible consommation de puissance pour un contrôle intégré, hautement re-configurabe pour un ajustement facile des performances de contrôle, et facilement prédictible pour fournir une idée précise sur les ressources logiques nécessaires avant l'implémentation même.L'exploration d'un certain nombre d'arithmétiques binaires a montré que l'arithmétique radix-2r est celle qui répond au mieux aux exigences précitées. Elle a été pleinement exploitée afin de concevoir des circuits de multiplication efficaces, qui sont au fait, le véritable moteur des systèmes linéaires.L'arithmétique radix-2r a été appliquée à l'intégration hardware de deux structures linéaires à taille de mot finie: un contrôleur PID variant dans le temps et à un contrôleur LQG invariant dans le temps,avec un filtre de Kalman. Le contrôleur PID a montré une nette supériorité sur ses homologues existants. Quant au contrôleur LQG, une réduction très importante des ressources logiques a été obtenue par rapport à sa forme initiale non optimisée / This thesis addresses the problem of optimal hardware-realization of finite-word-length(FWL) linear controllers dedicated to MEMS applications. The biggest challenge is to ensuresatisfactory control performances with a minimal hardware. To come up, two distinct butcomplementary optimizations can be undertaken: in control theory and in binary arithmetic. Only thelatter is involved in this work.Because MEMS applications are targeted, the binary arithmetic must be fast enough to cope withthe rapid dynamic of MEMS; power-efficient for an embedded control; highly scalable for an easyadjustment of the control performances; and easily predictable to provide a precise idea on therequired logic resources before the implementation.The exploration of a number of binary arithmetics showed that radix-2r is the best candidate that fitsthe aforementioned requirements. It has been fully exploited to designing efficient multiplier cores,which are the real engine of the linear systems.The radix-2r arithmetic was applied to the hardware integration of two FWL structures: a linear timevariant PID controller and a linear time invariant LQG controller with a Kalman filter. Both controllersshowed a clear superiority over their existing counterparts, or in comparison to their initial forms.