This thesis presents the development of a new method for incorporating station related outages in composite or bulk system reliability analysis. Station related failures can cause multiple component outages that can propagate to other parts of the network resulting in severe damages. In order to minimize the effects of station related outages on the composite system performance it is necessary for the designer to assess their effects. This task can be achieved by including station related outages in the composite system evaluation. Monte Carlo simulation is used in this research to assess composite system reliability. The new method described in this thesis is used to include station related outages in the reliability evaluation of two composite test systems. This new method is relatively simple and can be used to consider multiple component outages due to station related failures in composite system reliability evaluation. In this approach, the effects of station related outages are combined with the connected terminal failure parameters. Reliability studies conducted on the two composite test systems demonstrates that station failures significantly affect the system performance. The system reliability can be improved by selecting appropriate station configurations. This is illustrated by application to the two composite test systems.

In personnel selection, employment tests are intended to reduce selection errors and increase mean performance. The current thesis examines the impact of psychometric properties of the predictors on selection accuracy, or the consistency between selection on observed scores versus true scores. Implications for validity and subsequent levels of job performance, or prediction accuracy, are also examined in light of common top-down personnel selection procedures. Results reflect the importance of having reliable and valid predictor measures; the work also extends ideas in the area of utility analysis.

ESD, the discharge of electrostatically generated charges into an IC, is one of the most important reliability problems for ultra-scaled devices. This electrostatic charge can generate voltages of up to tens of kilovolts. These very high voltages can generate very high electric fields and currents across semiconductor devices, which may result in dielectric damage or melting of semiconductors and contacts. It has been reported that up to 70% of IC failures are caused by ESD. Therefore, it’s necessary to design a protection circuit for each pin that discharges the ESD energy to the ground. As the devices are continuously scaling down, while ESD energy remains the same, they become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Providing a complete ESD immunity for any circuit involves the design of proper protection circuits for I/O pins in addition to an ESD clamp between power supply pins. In this research both of these aspects are investigated and optimized solutions for them are reported. As Silicon Controlled Rectifier (SCR) has the highest ESD protection level per unit area, ESD protection for I/O pins is provided by optimizing the first breakdown voltage and latch-up immunity of SCR family devices. The triggering voltage of SCR is reduced by a new implementation of gate-substrate triggering technique. Furthermore, a new device based on SCR with internal darlington pair is introduced that can provide ESD protection with very small parasitic capacitance. Besides reducing triggering voltage, latch-up immunity of SCR devices is improved using two novel techniques to increase the holding voltage and the holding current. ESD protection between power rails is provided with transient clamps in which the triggering circuit keeps the clamp “on” during the ESD event. In this research, two new clamps are reported that enhance the triggering circuit of the clamp. The first method uses a CMOS thyristor element to provide enough delay time while the second method uses a flip flop to latch the clamp into “on” state at the ESD event. Moreover, the stability of transient clamps is analyzed and it’s been shown that the two proposed clamps have the highest stability compared to other state of the art ESD clamps. Finally, in order to investigate the impact of ESD protection circuits on high speed applications a current mode logic (CML) driver is designed in 0.13μm CMOS technology. The protection for this driver is provided using both MOS-based and SCR-based protection methods. Measurement results show that, compared to MOS-based protection, SCR-based protection has less impact on the driver performance due to its lower parasitic capacitance.

Wire bond reliability testing typically consists of aging bonds in a high temperature environment for long time periods, and removing samples at intervals to assess bond shear strength and characterize the bond cross sections. In this way, the degradation of the bond can be monitored at discrete time intervals, and it is determined whether the bond will be reliable during the specific service life. This process can be labour and time intensive. An alternative method is reported using an existing test chip that allows for contact resistance measurements and provides signals from piezoresistive integrated CMOS microsensors located around test bond pads. The sensors are sensitive to radial compressive or tensile stresses occurring on the bond pad due to intermetallic formation, oxidation, and crack formation at the bond interface. Two sets of identical test chips are bonded with optimized Au ball bonds and aged for 2000 h at 175 ºC. One set is connected to equipment which monitors signals from the stress sensors and the contact resistance of the bonds. The other set is destructively tested by shear tests and cross sectioning. It is found that the stress sensors are capable of indicating which stage of bond aging is experienced by relating the signal to the relative density of the intermetallic compounds (IMCs) and oxide which form during aging. This research offers a valuable new method for accelerating bond process development. By using the sensors to determine the stage of aging experienced and the magnitude of changes happening to the bond, the initial bond quality and bond reliability can be roughly characterized. A useful application is in comparing large samples of bonds made under varying conditions, and determining relative reliabilities of the bonds. A small sample size is required, as the sensors allow for complete continuous aging histories of individual bonds, which was not previously possible. A new test chip is designed for use in future studies which allows for contact resistance measurement, and provides stress signals for up to 55 bonds. A multiplexer integrated on the chip allows for measurements from one specified bond pad at a time. The chip is also equipped with x and yforce measurements which can be used to monitor bond process, and a resistive temperature detector for temperature measurement. A miniaturized bond aging system is designed to facilitate future works where chips are subject to high temperature storage. A heating element fits over the cavity of a microelectronic package containing the test chip, and allows for precise temperature control, while using less power than a conventional oven, and maintaining a low temperature at electrical connections to the package.

Bridges are the most critical components of the transportation network. The functionality of bridges is important for hurricane aftermath recovery and emergency activities. However, past hurricane events revealed the potential susceptibility of these bridges under storm induced wave and surge loads. Coastal bridges traditionally were not designed to sustain hurricane induced wave and surge loads; and furthermore, no reliability assessment tool exists for bridges exposed to this hazard. However, such a tool is imperative for decision makers to evaluate the risk posed to the existing bridge inventory, and to decide on the retrofit measures and mitigation strategies. This dissertation offers a first attempt to quantify the structural vulnerability of bridges under coastal storms, offering a probabilistic framework, input tools, and application illustrations. To accomplish this goal, first an unbiased wave load model is developed based on the existing wave load models in the literature. The biased is removed from the load models through statistical analysis of the experimental test data. The developed wave load model is used to evaluate the response of coastal bridges employing single-physics domain Dynamic numerical models. Additionally, a high fidelity fluid-structure interaction model is developed to take into account the significant intricacies, such as turbulence, wave diffraction, and air entrapment, as well as material and geometric nonlinearities in structure. This numerical model provides insight on the influential parameters that affect the response of coastal bridges. Moreover, a Monte Carlo based Static Model methodology is developed to enable fast evaluation of the bridge deck unseating mode of failure. This methodology can be used for fast screening of vulnerable structures under hurricane induced wave and surge loads in a large bridge inventory. New statistical learning tools are used to develop fragility surfaces for coastal bridges vulnerable to storms. The performance of each of these tools is evaluated and compared. The statistical learning approaches are used to enable reliability assessment using the more rigorous finite element models such as the Dynamic and FSI Models which is important for improved confidence and retrofit assessment. Additionally, a new systematic method to evaluate the limit state capacity functions based on the post-event global performance of the bridge structure is developed. The application of the developed reliability models is illustrated by utilizing them for Houston/Galveston Bay area bridge inventory. The case study of Houston/Galveston Bay area reveals that more than 30% of bridges have a high probability of failure during an extreme hurricane scenario event. Two vulnerable bridge structures from the case study are selected to investigate the effect of different potential retrofit measures. Recommendations are made for the most appropriate retrofit measures that can prevent the deck unseating without significantly increasing the structural demands on other components.

Risk management has become a key ingredient for businesses all over the world. High Reliability Organizations (HRO) has distinguished themselves as experts in this area. By continuously focusing on improving their ability to manage risks they’ve been able to successfully avoid catastrophes in environments where normal accidents can be expected due to complexity and risk factors.The aim of the thesis is to improve the risk management at Apotekens Service by applying theories from HRO and safety culture. In July 2009, following the re-regulation of the Swedish pharmacy market, Apotekens Service AB was appointed national pharmacy infrastructure supplier for the Swedish health care system. The market's direction and scope gives rise to a complex socio- technical environment that places high demands on the company's risk handling activities. By mapping the principles behind the success of HROs against methods used today, the thesis develops a foundation for how companies like Apotekens Service can manage risk efficiently.The analysis shows that there are great opportunities for Apotekens Service to apply theories of HRO and safety culture to improve their risk management.The company already has a positive safety culture, which is a prerequisite for maintaining safety over time. By mapping out the organization’s internal system dependencies, perform a threat analysis and develop an effective information management system Apotekens Service will improve the internal transparency whilst strengthening the possibilities for learning and effective communication. Finally, the thesis presents three risk management tools for assessing risk and reviewing the company’s ongoing work in the area.

ESD, the discharge of electrostatically generated charges into an IC, is one of the most important reliability problems for ultra-scaled devices. This electrostatic charge can generate voltages of up to tens of kilovolts. These very high voltages can generate very high electric fields and currents across semiconductor devices, which may result in dielectric damage or melting of semiconductors and contacts. It has been reported that up to 70% of IC failures are caused by ESD. Therefore, it’s necessary to design a protection circuit for each pin that discharges the ESD energy to the ground. As the devices are continuously scaling down, while ESD energy remains the same, they become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Providing a complete ESD immunity for any circuit involves the design of proper protection circuits for I/O pins in addition to an ESD clamp between power supply pins. In this research both of these aspects are investigated and optimized solutions for them are reported. As Silicon Controlled Rectifier (SCR) has the highest ESD protection level per unit area, ESD protection for I/O pins is provided by optimizing the first breakdown voltage and latch-up immunity of SCR family devices. The triggering voltage of SCR is reduced by a new implementation of gate-substrate triggering technique. Furthermore, a new device based on SCR with internal darlington pair is introduced that can provide ESD protection with very small parasitic capacitance. Besides reducing triggering voltage, latch-up immunity of SCR devices is improved using two novel techniques to increase the holding voltage and the holding current. ESD protection between power rails is provided with transient clamps in which the triggering circuit keeps the clamp “on” during the ESD event. In this research, two new clamps are reported that enhance the triggering circuit of the clamp. The first method uses a CMOS thyristor element to provide enough delay time while the second method uses a flip flop to latch the clamp into “on” state at the ESD event. Moreover, the stability of transient clamps is analyzed and it’s been shown that the two proposed clamps have the highest stability compared to other state of the art ESD clamps. Finally, in order to investigate the impact of ESD protection circuits on high speed applications a current mode logic (CML) driver is designed in 0.13μm CMOS technology. The protection for this driver is provided using both MOS-based and SCR-based protection methods. Measurement results show that, compared to MOS-based protection, SCR-based protection has less impact on the driver performance due to its lower parasitic capacitance.

Wire bond reliability testing typically consists of aging bonds in a high temperature environment for long time periods, and removing samples at intervals to assess bond shear strength and characterize the bond cross sections. In this way, the degradation of the bond can be monitored at discrete time intervals, and it is determined whether the bond will be reliable during the specific service life. This process can be labour and time intensive. An alternative method is reported using an existing test chip that allows for contact resistance measurements and provides signals from piezoresistive integrated CMOS microsensors located around test bond pads. The sensors are sensitive to radial compressive or tensile stresses occurring on the bond pad due to intermetallic formation, oxidation, and crack formation at the bond interface. Two sets of identical test chips are bonded with optimized Au ball bonds and aged for 2000 h at 175 ºC. One set is connected to equipment which monitors signals from the stress sensors and the contact resistance of the bonds. The other set is destructively tested by shear tests and cross sectioning. It is found that the stress sensors are capable of indicating which stage of bond aging is experienced by relating the signal to the relative density of the intermetallic compounds (IMCs) and oxide which form during aging. This research offers a valuable new method for accelerating bond process development. By using the sensors to determine the stage of aging experienced and the magnitude of changes happening to the bond, the initial bond quality and bond reliability can be roughly characterized. A useful application is in comparing large samples of bonds made under varying conditions, and determining relative reliabilities of the bonds. A small sample size is required, as the sensors allow for complete continuous aging histories of individual bonds, which was not previously possible. A new test chip is designed for use in future studies which allows for contact resistance measurement, and provides stress signals for up to 55 bonds. A multiplexer integrated on the chip allows for measurements from one specified bond pad at a time. The chip is also equipped with x and yforce measurements which can be used to monitor bond process, and a resistive temperature detector for temperature measurement. A miniaturized bond aging system is designed to facilitate future works where chips are subject to high temperature storage. A heating element fits over the cavity of a microelectronic package containing the test chip, and allows for precise temperature control, while using less power than a conventional oven, and maintaining a low temperature at electrical connections to the package.

Detecting ambiguity is essential for successful communication. Two studies investigated whether preschool- (4- to 5-year-old) and school-age (6- to 7-year-old) children show sensitivity to communicative ambiguity and can use this cue to determine which speakers constitute valuable informational sources. Children were provided clues to the location of hidden dots by speakers who varied in clarity and accuracy. Subsequently, children decided from whom they would like to receive additional information. In Study 1, preschool- (n=40) and school-age (n=42) children preferred to solicit information from unambiguous than from ambiguous speakers. However, ambiguous speakers were preferred to speakers who provided inaccurate information. In Study 2, when not provided with information about the outcome of the speakers’ clues, school-age (n=22), but not preschool-age (n=19), children preferred unambiguous relative to ambiguous speakers. Results highlight a developmental progression in children’s use of communicative ambiguity as a cue to determining which individuals are preferable informants.

The primary function of a power system is to supply its customers with electrical energy as economically as possible and with acceptable reliability and quality. Generating capacity adequacy evaluation is the oldest and most extensively studied aspect of power system reliability assessment. A wide range of methods have been developed to perform this evaluation. Two computer programs were developed based on the analytical and simulation techniques and used as tools in this research work. A number of basic considerations in generating capacity adequacy evaluation are investigated. Generating unit residence time distributions and peaking load units are incorporated in the analysis.<p> Two commonly encountered misconceptions regarding the basic system reliability indices are examined by applying the two programs to two reliability test systems. Reliability index probability distributions can be used to supplement the information provided by the expected index values. The concept of creating distributions and the additional information that can be obtained is illustrated in this thesis. <p> Generating unit residence time distributions are generally categorized as being either exponential or non-exponential in form. The exponential distribution is utilized, however, in virtually all practical system studies. The impacts on the system reliability of non-exponential unit state residence time distributions are examined in this research. <p> Peaking load units and base load units have different operating characteristics. The functions of peaking load units vary with changes in the system operating conditions. This is examined in this research. <p>The conclusions and techniques presented in this thesis should prove valuable in power system planning and operation.