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International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / The UTTR (Utah Test & Training Range) offers the largest over land test and training airspace in the continental United States. It provides excellent telemetry data processing capability through a number of TM (telemetry) sites. Selecting the best source of telemetry data for optimum coverage from these many sites can be very involved and challenging for ground station personnel. Computer-based best source selection automates this process, thereby increasing accuracy and efficiency. This paper discusses the capabilities of the BTSS (Best Telemetry Source Selector), its background, design and development, applications, and future at the UTTR.

Virtualization is becoming more and more popular since the hardware that is available today often has theability to run more than just a single machine. The hardware is too powerful in relation to the requirementsof the software that is supposed to run on the hardware, making it inefficient to run too little software ontoo powerful of machines. With virtualization, the ability exists to run a lot of different software on thesame hardware, thereby increasing the efficiency of hardware usage.Virtualization doesn't stop at just virtualizing operating systems or commodity software, but can also beused to virtualize networking components. These networking components include everything from routersto switches and are possible to set up on any kind of virtulized system.When discussing virtualization of networking components, the experssion “Software Defined Networking”is hard to miss. Software Defined Networking is a definition that contains all of these virtualized networkingcomponents and is the expression that should be used when researching further into this subject. There'san increasing interest in these virtualized networking components now in relation to just a few years ago.This is due to company networking becoming much more complex now in relation to the complexity thatcould be found in a network a few years back. More services need to be up inside of the network and a lotof people believe that Software Defined Networking can help in this regard.This thesis aim is to try to find out what kind of differences there are between multiple different softwarerouters. Finding out things like, which one of the routers that offer the highest network speed for the leastamount of hardware cost, are the kind of things that this thesis will be focused on. It will also look at somedifferent aspects of performance that the routers offer in relation to one another in order to try toestablish if there exists any kind of “best” router in multiple different areas.The idea is to build up a virtualized network that somewhat relates to how a normal network looks insmaller companies today. This network will then be used for different types of testing while having thesoftware based router placed in the middle and having it take care of routing between different local virtualnetworks. All of the routers will be placed on the same server and their configuration will be very basicwhile also making sure that each of the routers get access to the same amount of hardware.After initial testing, all routers that perform bad will be opted out for additional testing. This is done tomake sure that there's no unnecessary testing done on routers that seem to not be able to keep up withthe other ones. The results from these tests will be compared to the results of a hardware router with thesame kind of tests used with it in the middle in relation to the tests the software routers had to go through.The results from the testing were fairly surprising, only having one single router being eliminated early onas the remaining ones continued to “battle” one another with more tests. These tests were compared tothe results of a hardware router and the results here were also quite surprising with a much betterperformance in many different areas from the software routers perspective.

Applications with timing requirements, such as multimedia and live multi-user interaction, are becoming more prevalent in wide area networks. The desire to provide more predictable performance for such applications in packet switched wide area networks is evident in the channel management provided by Asynchronous Transfer Mode (ATM) networks and in the extensions to the Internet protocols proposed by the Internet Engineering Task Force (IETF) working groups on integrated and differentiated service. The ability to provide guarantees on the performance of traffic flows, such as packet delay and loss characteristics, relies on an accurate model of the traffic arrival and service at each node in the network. This thesis surveys the work in bounding packet delay based on various proposed queuing disciplines and proposes a method for more accurately defining the traffic arrival and worst case backlog experienced by packets. The methods are applied to the first in first out (FIFO) queuing discipline to define equations for determining the worst case backlog and queuing delay in multihop networks. Simulation results show a significant improvement in the accuracy of the delay bounds over existing bounds published in the literature. An improvement of two orders of magnitude can be realised for a ten hop path and the improvement increases exponentially with the length of the path for variable rate network traffic. The equations derived in the thesis also take into consideration the effect of jitter on delay, thereby removing the requirement for rate controllers or traffic shaping within the network. In addition to providing more accurate delay bounds, the problem of providing fault tolerance to channels with guaranteed quality of service (QoS) is also explored. This thesis introduces a method for interleaving resource requirements of backup channels to reduce the overall resource reservations that are required to provide guaranteed fault recovery with the same QoS as the original failed channel. An algorithm for selecting recovery paths that can meet a channel's QoS requirements during recovery is also introduced. / Thesis (Ph.D.)--Computer Science, 2003.

<p>The computer engineering group at Linköping University has parts of their research dedicated to networks-on-chip and components used in network components and terminals. This research has among others resulted in the SoCBUS NOC and a flow based network protocol processor. The main objective of this project was to integrate these components into an IP router with two or more Gigabit Ethernet interfaces.</p><p>A working system has been designed and found working. It consists of three main components, the input module, the output module and a packet buffer. Due to the time constraint and the size of the project the packet buffer could not be designed to be as efficient as possible, thus reducing the overall performance. The SoCBUS also has negative impact on performance, although this could probably be reduced with a revised system design. If such a project is carried out it could use the input and output modules from this project, which connect to SoCBUS and can easily be integrated with other packet buffers and system designs.</p>

<p>The computer engineering department at Linköping University has a research project which investigates the use of an on-chip network in a router. There has been an implementation of it in a FPGA and for this router there is a need for buffer memory. This thesis extends the router design with a DDR memory controller which uses the features provided by the Virtex-II FPGA family.</p><p>The thesis shows that by carefully scheduling the DDR SDRAM memory high volume transfers are possible and the memory can be used quite effciently despite its rather complex interface.</p><p>The DDR memory controller developed is part of a packet buffer module which is integrated and tested with a previous, slightly modifed, FPGA based router design. The performance of this router is investigated using real network interfaces and due to the poor network performance of desktop computers special hardware is developed for this purpose.</p>

The Internet grows extremely fast in terms of number of users and traffic volume, as well as in the number of services that must be supported. This development results in new requirements on routers—the main building blocks of the Internet. Existing router designs suffer from architectural limitations that make it difficult to meet future requirements, and the purpose of this thesis is to explore new ways of building routers. We take the approach to investigate distributed and modular router designs, where routers are composed of multiple modules that can be mapped onto different processing elements. The modules communicate through open well-defined interfaces over an internal network. Our overall hypothesis is that such a combination of modularization and decentralization is a promising way to improve scalability, flexibility, and robustness of Internet routers—properties that will be critical for new generations of routers. Our research methodology is based on design, implementation, and experimental verification. The design work has two main results: an overall system design and a distributed router control plane. The system design consists of interfaces, protocols, and internal mechanisms for physically separation of different components of a router. The distributed control plane is a decomposition of control software into independent modules mapped onto multiple distributed processing elements. Our design is evaluated and verified through the implementation of a prototype system. The experimental part of the work deals with two key issues. First, transport mechanisms for communication of internal control information between processing elements are evaluated. In particular, we investigate the use of reliable multicast protocols in this context. Results regarding communication overhead as well as overall performance of routing table dissemination and installation are presented. The results show that even though there are certain costs associated with using reliable multicast, there are large performance gains to be made when the number of processing elements increases. Second, we present performance results of processing routing information in a distributed control plane. These results show that the processing time can be significantly reduced by distributing the workload over multiple processing elements. This indicates that considerable performance improvements can be made through the use of the distributed control plane architecture proposed in this thesis. / QC 20100616

The Pixel Router was developed at the University of Kentucky with the intent of supporting multi-projector displays by combining the scalability of commercial software solutions with the flexibility of commercial hardware solutions. This custom hardware solution uses a Look Up Table for an arbitrary input to output pixel mapping, but suffers from high memory latencies due to random SDRAM accesses. In order for this device to achieve marketability, the image interpolation method needed improvement as well. The previous design used the nearest neighbor interpolation method, which produces poor looking results but requires the least amount of memory accesses. A cache was implemented to support bilinear interpolation to simultaneously increase the output frame rate and image quality. A number of software simulations were conducted to test and refine the cache design, and these results were verified by testing the implementation on hardware. The frame rate was improved by a factor of 6 versus bilinear interpolation on the previous design, and by as much as 50% versus nearest neighbor on the previous design. The Pixel Router was also certified for FCC conducted and radiated emissions compliance, and potential commercial market areas were explored.

Recently, various special purpose processors have been developed and are frequently being used for different specialized tasks. Prominent among these are the communication processors, which are generally used within an embedded system environment. Such processors can run relatively advanced and general purpose operating systems such as uCLinux, which is a freely available embedded Linux distribution. In this work, a prototype SoHo (Small office / Home office) router is designed and implemented using Motorola MCF5272 as the core communication processor and uCLinux as the operating system. The implementation relies purely on the existing hardware resources of an available development board and the publicly available open source utilities of uCLinux. The overall development process provides an embedded system implementation and configuration example.

Applications with timing requirements, such as multimedia and live multi-user interaction, are becoming more prevalent in wide area networks. The desire to provide more predictable performance for such applications in packet switched wide area networks is evident in the channel management provided by Asynchronous Transfer Mode (ATM) networks and in the extensions to the Internet protocols proposed by the Internet Engineering Task Force (IETF) working groups on integrated and differentiated service. The ability to provide guarantees on the performance of traffic flows, such as packet delay and loss characteristics, relies on an accurate model of the traffic arrival and service at each node in the network. This thesis surveys the work in bounding packet delay based on various proposed queuing disciplines and proposes a method for more accurately defining the traffic arrival and worst case backlog experienced by packets. The methods are applied to the first in first out (FIFO) queuing discipline to define equations for determining the worst case backlog and queuing delay in multihop networks. Simulation results show a significant improvement in the accuracy of the delay bounds over existing bounds published in the literature. An improvement of two orders of magnitude can be realised for a ten hop path and the improvement increases exponentially with the length of the path for variable rate network traffic. The equations derived in the thesis also take into consideration the effect of jitter on delay, thereby removing the requirement for rate controllers or traffic shaping within the network. In addition to providing more accurate delay bounds, the problem of providing fault tolerance to channels with guaranteed quality of service (QoS) is also explored. This thesis introduces a method for interleaving resource requirements of backup channels to reduce the overall resource reservations that are required to provide guaranteed fault recovery with the same QoS as the original failed channel. An algorithm for selecting recovery paths that can meet a channel's QoS requirements during recovery is also introduced. / Thesis (Ph.D.)--Computer Science, 2003.