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Passive radar is a technology for detection of targets using echoes of existing radio transmitter, such as FM-radio. Since only receivers are needed for operation, a passive radar system has the possibility of being implemented using low-cost hardware. Using lower cost implementations to cover blind-spots of other, more sophisticated systems, could be a viable solution for full radar coverage. To achieve this, an understanding of the effects such low-cost systems have on the performance of a radar is needed.  A prominent problem for passive radar is that the interference caused by the direct signal from the transmitter used and reflections from uninteresting terrain, called clutter, can drown out the echoes from targets. This thesis compares the direct signal interference (DSI) suppression algorithms: ECA, ECA-S, ECA-B, NLMS and FBNLMS when run on data from a low-cost receiver called KerberosSDR. It is found that the low ADC resolution of 8 bits is a limiting factor for KerberosSDR. Random noise in the receiver can also limit the performance. None of the tested algorithms are any more or less affected by the ADC resolution or the noise. The first difference appears when comparing the execution times, where FBNLMS is 10–20 times faster than the other algorithms. However, the slower rate of convergence for FBNLMS and NLMS causes them to lose performance in environments where the DSI and clutter are considerably stronger than the target echoes. The algorithms FBNLMS and NLMS also lose performance due to their inability to model frequency shifted echoes as unwanted. The main disadvantages of ECA, ECA-B and ECA-S are their long execution time. It is concluded that FBNLMS would be the best candidate in most cases for low-cost hardware, as it allows execution on slower hardware and the main disadvantages not being too prominent in the use case of covering blind-spots of other systems.

L’utilisation de matrice de portes logiques reconfigurables (FPGA) est une des seules solutionspour traiter des flux de plusieurs 100 MÉchantillons/seconde en temps-réel. Toutefois, ce typede composant présente une grande difficulté de mise en oeuvre : au delà d’un type langage spécifique,c’est tout un environnement matériel et une certaine expérience qui sont requis pourobtenir les traitements les plus efficaces. Afin de contourner cette difficulté, de nombreux travauxont été réalisés dans le but de proposer des solutions qui, partant d’un code écrit dans unlangage de haut-niveau, vont produire un code dans un langage dédié aux FPGAs. Nos travaux,suivant l’approche d’assemblage de blocs et en suivant la méthode du skeleton, ont visé à mettreen place un logiciel, nommé CoGen, permettant, à partir de codes déjà développés et validés,de construire des chaînes de traitements en tenant compte des caractéristiques du FPGA cible,du débit entrant et sortant de chaque bloc pour garantir l’obtention d’une solution la plus adaptéepossible aux besoins et contraintes. Les implémentations des blocs de traitements sont soitgénérés automatiquement soit manuellement. Les entrées-sorties de chaque bloc doivent respecterune norme pour être exploitable dans l’outil. Le développeur doit fournir une descriptionconcernant les ressources nécessaires et les limitations du débit de données pouvant être traitées.CoGen fournit à l’utilisateur moins expérimenté une méthode d’assemblage de ces blocsgarantissant le synchronisme et cohérence des flux de données ainsi que la capacité à synthétiserle code sur les ressources matérielles accessibles. Cette méthodologie de travail est appliquéeà des traitements sur des flux vidéos (seuillage, détection de contours et analyse des modespropres d’un diapason) et sur des flux radio-fréquences (interrogation d’un capteur sans-fils parméthode RADAR, réception d’un flux modulé en fréquence, et finalement implémentation deblocs de bases pour déporter le maximum de traitements en numérique). / Using Field Programmable Gate Arrays (FPGA) is one of the very few solution for real time processingdata flows of several hundreds of Msamples/second. However, using such componentsis technically challenging beyond the need to become familiar with a new kind of dedicateddescription language and ways of describing algorithms, understanding the hardware behaviouris mandatory for implementing efficient processing solutions. In order to circumvent these difficulties,past researches have focused on providing solutions which, starting from a description ofan algorithm in a high-abstraction level language, generetes a description appropriate for FPGAconfiguration. Our contribution, following the strategy of block assembly based on the skeletonmethod, aimed at providing a software environment called CoGen for assembling various implementationsof readily available and validated processing blocks. The resulting processing chainis optimized by including FPGA hardware characteristics, and input and output bandwidths ofeach block in order to provide solution fitting best the requirements and constraints. Each processingblock implementation is either generated automatically or manually, but must complywith some constraints in order to be usable by our tool. In addition, each block developer mustprovide a standardized description of the block including required resources and data processingbandwidth limitations. CoGen then provides to the less experienced user the means to assemblethese blocks ensuring synchronism and consistency of data flow as well as the ability to synthesizethe processing chain in the available hardware resources. This working method has beenapplied to video data flow processing (threshold, contour detection and tuning fork eigenmodesanalysis) and on radiofrequency data flow (wireless interrogation of sensors through a RADARsystem, software processing of a frequency modulated stream, software defined radio).

The exponential growth of research and deployment of 5G networks has led to an increased interest in massive Machine Type Communications (mMTC), as we are on the quest to connect all devices. This can be attributed to the constant development of long-distance and low-powered Internet-of- Things (IoT) technologies, or, Low Power Wide Area Network (LPWAN) technologies such as Long-Range (LoRa) and Narrow Band- IoT (NB-IoT). These technologies are gaining prominence in the IoT domain as the number of LPWAN connected devices has doubled from 2018 to 2019. This increase in devices warrants a proportional number of gateways to push the data to the Internet for further analytics. The traditional LPWAN architectures do not provide dynamic scaling of resources or energy-efficient solutions. Thus, a Cloud-Native (CN) split architecture based on the functional characteristics of the components is a necessity. In this work, a software-based implementation of the LoRa stack on GNU Radio is designed and implemented using Software-Defined Radio (SDR). The LoRa gateway is implemented in software completely, replicating the functions of the hardware for communicating with any LoRa Network Server. Several experiments with different setups have been performed on the testbed to measure the resource utilization and packet delay of the LoRa Physical (PHY) and Medium Access Control (MAC) layers. Also, the testbed has been moved into Docker containers to emulate a cloud-based platform and make the transition faster. Higher throughput and lower delay (Improvement in the range of 1.3x - 6.7x) were recorded upon splitting the testbed into Radio Head (RH) and Edge containers. Finally, three potential functional split architectures including the gateway have been discussed while providing a fair trade-off between pooling gain and consumed bandwidth for a CN split architecture. / Den exponentiella tillväxten av forskning och distribution av 5G-nät har lett till ett ökat intresse för massive Machine Type Communicationsn (mMTC) eftersom vi är på jakt att ansluta alla enheter. Detta kan tillskrivas den ständiga utvecklingen av långdistans- och lågdrivna Internet-of-Things-teknologier (IoT) -teknologier, eller, Low Power Wide Area Network (LPWAN) tekniker som Long-Range (LoRa) och Narrow Band- IoT (NB-IoT). Dessa teknologier blir framträdande inom IoT-domänen eftersom antalet LPWAN-anslutna enheter har fördubblats från 2018 till 2019. Denna ökning av enheterna motiverar ett proportionellt antal portar för att driva data till Internet för ytterligare analys. De traditionella LPWAN-arkitekturerna ger inte dynamisk skalning av resurser eller energieffektiva lösningar. Således är en moln-infödd delad arkitektur baserad på funktionernas egenskaper hos komponenterna en nödvändighet. I detta arbete designas och implementeras en programvarubaserad implementering av LoRa-stacken på GNU Radio med hjälp av Software- Defined Radio (SDR). LoRa-gatewayen implementeras i mjukvara fullständigt, vilket replikerar maskinvarans funktioner för att kommunicera med någon LoRaNetwork Server. Flera experiment med olika inställningar har utförts på testbädden för att mäta resursutnyttjandet och paketfördröjningen för LoRa Physical (PHY) och Medium Access Control (MAC) -skikten. Testbädden har också flyttats in i Docker-behållare för att emulera en molnbaserad plattform och göra övergången snabbare. Högre genomströmning och lägre fördröjning (Förbättring inom intervallet 1,3x - 6,7x) registrerades vid uppdelning av testbädden i Radio Head (RH) och Edge containrar. Slutligen har tre potentiella funktionella splitarkitekturer inklusive gateway diskuterats samtidigt som det ger en rättvis avvägning mellan pooling av vinst och förbrukad bandbredd.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / The ISM bands have opened up new opportunities for telemetry using spread-spectrum communications. A low-cost frequency-hopping radio is described here for the 900 MHz ISM band that can be programmed with a wide range of hop and data rates. The ‘C6201 DSP from TI is used to control the frequency and data rate of the TI TRF6900 transceiver chip using a custom interface of the 6201 EVM board to the serial I/O on the 6900 evaluation board.