Habilitationsschrift--Theologische Fakultät--Zürich, 1994. / Bibliogr. p. 239-241. Index.

abstract: Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250&degC.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235&degC.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage. / Dissertation/Thesis / M.S. Electrical Engineering 2010

The purpose of this project has been twofold: firstly, to develop further FTIR reflectance spectroscopy as a technique for the quantitative characterisation of SOI multilayer structures and secondly, to use it in combination with other techniques, such as RBS/Channelling, XTEM, SIMS, AES and SRP, to investigate the evolution and structure of novel SOI materials. In order to evaluate the FTIR results, many SIMOX samples were fabricated with a wide range of Si and buried SiO2 layer thicknesses with one or two buried oxide layers. The FTIR results are compared to those obtained with the other experimental techniques and with theoretical calculations. We show that, given an "a priori" knowledge of the structure which is used to define the initial structural model, FTIR can be used as a non-destructive, fast, and inexpensive control method for characterising SOI structures. FTIR offers +/-2 nm accuracy in layer thicknesses and +/-5 nm in interfacial region thicknesses, over a wide (0.5 to >10mum) depth range, while for shallower depths an error of 15% on average is likely. FTIR gives Si thickness values which are within 5%, and buried layer or interfacial region thickness values which are within 10% to 20%, from the values obtained by other techniques. The sensitivity to oxygen content variations is down to 5 x 1020 O cm-3 for the top of a Gaussian profile, and 1 X 1022 O cm-3 over a 20 nm thick layer. FTIR gives a value for the retained dose within 5% of the nominal dose for both unannealed and annealed samples. Novel SOI materials, such as deep buried oxide layers and double SIMOX structures were fabricated and characterised, and the processing parameters optimised. We show that, for 2 MeV oxygen implantation into Si at 700°C to a dose of 2 x 1018 O+ cm-2 and after annealing at 1300°C for 6 hours, a buried layer is formed which is continuous but contains Si islands. It is found that by increasing the annealing time to 12 hours, the homogeneity of the buried layer is improved. We propose that an increase of both the oxygen dose and the annealing temperature would result in a higher quality buried oxide layer. The adverse effect of high beam current densities to the sample structure after annealing is demonstrated for the high energy SIMOX samples. We show that double SIMOX structures can be fabricated by a three step process, with one only annealing step at the end. Such structures can be used for Si waveguiding applications and we present preliminary results of waveguiding loss measurements, where a value of 18 dB/cm was obtained.

L'introspection est souvent contre-intuitive. Par exemple nous croyons, intuitivement, posséder un Moi mais, en réalité, aucun percept de ce "Moi" n'est possible. De plus, notre capacité à conceptualiser le Moi est tributaire des fonctions langagières. Ce que nous observons après analyse est que la conscience de soi-même, loin d'être innée, se développe progressivement en corrélation avec le développement du langage. Le concept de Soi se développe également ainsi. Plusieurs auteurs tendent à confirmer ce fait: la capacité de référer du sujet l'amène inconsciemment à prendre conscience de lui-même. L'autoréférence est donc le critère indispensable à l'émergence d'une conscience articulée de soi-même. À l'aide de différents ouvrages consacrés à l'étude de ce domaine, nous proposons une analyse de la présente question. Le principal objectif de cette thèse est d'étudier de plus près le développement de la conscience de soi à travers une analyse des différents stades de développement chez l'enfant. Nous voulons en évaluer les caractéristiques essentielles et confirmer le rôle prépondérant du langage interne dans la capacité à devenir à la fois conscients de soi-même mais également dans la capacité à se projeter dans l'avenir (maintien du "Soi" ou "Moi" temporel). Dans la dernière section de thèse nous voulons démontrer, à l'aide d'étude de cas empiriques, que certaines lésions, particulièrement relatives aux fonctions langagières, entraînent inexorablement des répercussions sur la conscience de soi. Ainsi nous confirmons l'hypothèse de départ: la conscience articulée de soi dépend du langage interne.

Thèse numérisée par la Direction des bibliothèques de l'Université de Montréal.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Thèse numérisée par la Direction des bibliothèques de l'Université de Montréal.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Este trabalho apresenta o estudo do efeito de Auto-Aquecimento (Self-Heating SH) em transistores Silicon-On-Insulator (SOI) com estrutura de canal gradual (GC SOI MOSFET). São apresentadas as características da tecnologia SOI e em especial as características do transistor GC-SOI MOSFET. Foi realizada uma análise do SH usando uma comparação de dispositivos SOI convencionais com GC SOI nMOSFET. Esta análise compara dispositivos com o mesmo comprimento de máscara do canal e dispositivos com o mesmo comprimento efetivo de canal. Simulações numéricas bidimensionais foram efetuadas nas duas análises considerando o aquecimento da rede cristalina. Os modelos e a constante térmica usados nestas simulações também foram apresentados. É demonstrado que os dispositivos GC com o mesmo comprimento de máscara do canal apresentam uma ocorrência similar de SH independentemente do comprimento da região menos dopada apesar de uma maior corrente de dreno. Por outro lado, para mesmo comprimento efetivo de canal o SH é menos pronunciado em transistores GC uma vez que o comprimento de máscara do canal é aumentado para compensar a diferença de corrente. Esta análise é realizada também variando-se a temperatura de 200K a 400K e resultados análogos foram observados apesar do efeito ser mais intenso em baixas temperaturas. / This work presents the study of Self-Heating (SH) effect in Graded-Channel Silicon-On-Insulator (GC SOI) nMOSFETs. The SOI technology characteristics are described with special attention to the GC SOI nMOSFET characteristics. A Self-Heating (SH) analysis was performed using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis was performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations were performed considering the lattice heating in both cases. The models and the thermal conductive constant used in these simulations are also presented. It has been demonstrated that conventional and GC devices with the same mask channel length present similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel lengths, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. This analysis is also carried through varying it temperature of 200K to 400K and analogous results had been observed despite the effect being more intense in low temperatures.

Este trabalho apresenta o estudo do efeito de Auto-Aquecimento (Self-Heating SH) em transistores Silicon-On-Insulator (SOI) com estrutura de canal gradual (GC SOI MOSFET). São apresentadas as características da tecnologia SOI e em especial as características do transistor GC-SOI MOSFET. Foi realizada uma análise do SH usando uma comparação de dispositivos SOI convencionais com GC SOI nMOSFET. Esta análise compara dispositivos com o mesmo comprimento de máscara do canal e dispositivos com o mesmo comprimento efetivo de canal. Simulações numéricas bidimensionais foram efetuadas nas duas análises considerando o aquecimento da rede cristalina. Os modelos e a constante térmica usados nestas simulações também foram apresentados. É demonstrado que os dispositivos GC com o mesmo comprimento de máscara do canal apresentam uma ocorrência similar de SH independentemente do comprimento da região menos dopada apesar de uma maior corrente de dreno. Por outro lado, para mesmo comprimento efetivo de canal o SH é menos pronunciado em transistores GC uma vez que o comprimento de máscara do canal é aumentado para compensar a diferença de corrente. Esta análise é realizada também variando-se a temperatura de 200K a 400K e resultados análogos foram observados apesar do efeito ser mais intenso em baixas temperaturas. / This work presents the study of Self-Heating (SH) effect in Graded-Channel Silicon-On-Insulator (GC SOI) nMOSFETs. The SOI technology characteristics are described with special attention to the GC SOI nMOSFET characteristics. A Self-Heating (SH) analysis was performed using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis was performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations were performed considering the lattice heating in both cases. The models and the thermal conductive constant used in these simulations are also presented. It has been demonstrated that conventional and GC devices with the same mask channel length present similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel lengths, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. This analysis is also carried through varying it temperature of 200K to 400K and analogous results had been observed despite the effect being more intense in low temperatures.