The subject of this paper is to the research and develop Liquid Crystal Display Module(LCM) test system for LCM factories.We prpose an FPGA,built in an NiosII soft CPU,as the control core with peripheral circuits to form a flexible SOPC¡]System on Programmable Chip¡^. Using this digital circuit being synthetic with the hardware description language, one can further integrate analog and digital peripheral devices by software control to establish a universal of medium and small LCM tester, and can conduct display function verification on such system. This system has been proved effectively to perform functional test for multi type LCM, and meanwhile it further demonstrates the advantage in its flexibility for configuration change due to its SOPC design.

Målet med examensarbetet är att implementera en mjuk CPU i en FPGA-krets som finns tillgänglig på ett ALTERA DE2 Board. Denna mjuka processor integreras i ett projekt skapat i utvecklingsmiljön Quartus II. Den kommunicera med programmerad logik i FPGA:n och den signalbehandlar en audiosignal (stereo), så att ett eko kan genereras och att volym och balans blir justerbar. Detta styrs av ett tangentbord som kopplas till DE2-kortet och de olika förändringarna på utsignalen visas på en LCD. / The ambition with this thesis is to implement a soft CPU i a FPGA-circuit which is available on an ALTERA DE2 Board. This soft processor is integrated in a project designed in the development environment: Quartus II CAD System. It communicates with programmed logic in the FPGA and it alters an audiosignal so that an eco is generated and so that volume and balance can be adjusted. This is controled from a keyboard which is connected to the DE2-card and all the different adjustments of the outsignal are shown on an LCD.

This research aims to discuss the integration of an 10/100 Ethernet MAC on a System-on-a-Programmble-Chip. SOPC is a chip combined with ¡§ASIC¡¨(Application Specific IC) and ¡§PLD¡¨(Programmable Logic Device). Due to the lower Complexity, SOPC is suitable for SOC study in academic. In this research, Altera ARM-based ExcaliburTM SOPC is used and an Opencore 10/100 Ethernet MAC is integrated onto it. The topic of SOPC architecture, SOPC development flow, bus interface design of the hardware, driver development and verification strategy of SOPC are discussed. This work is hopeful to be referable material for school SOPC teaching.

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Ciências da Saúde, Programa de Pós-Graduação em Ciências da Saúde, 2017. / Submitted by Priscilla Sousa (priscillasousa@bce.unb.br) on 2017-10-24T13:43:38Z No. of bitstreams: 1 2017_ClezioRodriguesdeCarvalhoAbreu.pdf: 1449794 bytes, checksum: 5f6320c8c9e1169ee627cb160fd98cb9 (MD5) / Approved for entry into archive by Raquel Viana (raquelviana@bce.unb.br) on 2017-10-25T16:57:11Z (GMT) No. of bitstreams: 1 2017_ClezioRodriguesdeCarvalhoAbreu.pdf: 1449794 bytes, checksum: 5f6320c8c9e1169ee627cb160fd98cb9 (MD5) / Made available in DSpace on 2017-10-25T16:57:11Z (GMT). No. of bitstreams: 1 2017_ClezioRodriguesdeCarvalhoAbreu.pdf: 1449794 bytes, checksum: 5f6320c8c9e1169ee627cb160fd98cb9 (MD5) Previous issue date: 2017-10-25 / A síndrome dos ovários policísticos (SOPC) tem grande importância clínica, uma vez que sua prevalência vem aumentando e que apresenta implicações clínicas significativas, incluindo reprodutivas, metabólicas e psicológicas. Sua etiologia é complexa e multifatorial, e envolve fatores genéticos, ambientais e comportamentais. Dados de alguns estudos observacionais sugerem a associação entre a exposição a desreguladores endócrinos (DEs) e sua ocorrência. Objetivo: Analisar, por meio de revisão sistemática de estudos observacionais em humanos, se há associação entre a exposição a DEs e a ocorrência de SOPC. Método: Foi realizada busca, nas bases de dados PubMed/Medline, Web of Science, Scopus, Lilacs e Biblioteca Cochrane, de estudos observacionais em humanos que analisaram a associação entre a exposição a DEs e a ocorrência de SOPC, e publicados até maio de 2017, sem restrição de língua. A busca foi efetuada pela combinação de termos relacionados aos DEs e à SOPC. A qualidade metodológica dos estudos foi avaliada com a utilização da escala de Newcastle-Ottawa. Resultados: Foram identificados 145 artigos que atenderam aos critérios de busca; destes, 7 estudos atenderam aos critérios de inclusão. Estes estudos, de corte transversal ou caso-controle, incluídos nessa revisão, investigaram a relação entre a exposição ao bisfenol A, compostos organoclorados (bifenilas policloradas e pesticidas organoclorados), compostos perfluorado, hidrocarbonetos aromáticos policíclicos e ftalatos e a ocorrência de SOPC. Em geral, houve uma associação positiva entre a exposição a estes DEs e a ocorrência da síndrome, e os estudos foram considerados de qualidade metodológica média a elevada. Conclusão: Os dados da presente revisão sugerem a associação entre a exposição a DEs e a ocorrência de SOPC. Entretanto, todos os estudos incluídos foram observacionais e transversais, não sendo possível estabelecer relação de causalidade entre a exposição a DEs e a SOPC. / Polycystic ovarian syndrome (PCOS) is of major clinical importance due to its increasing prevalence and its implications, including reproductive, metabolic, and psychological disturbances. Its etiology is complex and multifactorial, involving genetic, environmental and behavioral aspects. Data from observational studies suggest an association between exposure to endocrine dirsuptors (EDs) and the occurrence of PCOS. Objective: To systematically review human observational studies addressing the association between the exposure to EDs and PCOS. Methods: We searched Pubmed/Medline, Web of Science, Scopus, Lilacs and Cochrane Library for studies addressing the association between EDs and PCOS from inception until May 2017, with no language restriction. The searched was performed by combining search terms related to EDs and PCOS. The methodological quality of studies was assessed using the Newcastle-Ottawa scale. Results: We identified 145 citations and 7 met our inclusion criteria. The studies were cross-sectional or case-controle studies and investigated the association between bisphenol A, organochlorine compounds (polychlorinated bisphenyls and organochloride pesticides), polycyclic aromatic hydrocarbons and phthalates and PCOS occurrence. Overall, the studies indicated a positive association between exposure to EDs and PCOS. Most studies were considered of medium or high methodological quality. Conclusion: This systematic review indicates an association between exposure to EDs and the occurrence of PCOS. However, their cross-sectional design precludes establishing causality between EDs and PCOS.

O presente trabalho apresenta a implementação de um core de rede Ethernet 10/100Mbps com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. A tecnologia Ethernet foi implementada em computação reconfigurável e utilizou-se como base um módulo disponível na Internet denominado OpenCores MAC 10/100. O projeto foi desenvolvido para ser aplicado em sistemas embarcados, mais especificamente para o uso em um robô móvel em desenvolvimento no Laboratório de Computação Reconfigurável do ICMC/USP. O core foi incorporado à biblioteca da ferramenta SoPC Builder da Altera, visando uma fácil integração do mesmo em outros projetos. Foram utilizadas as ferramentas Quartus II e ModelSim para o desenvolvimento e testes do sistema, além de dois kits Nios versão Stratix para a validação do projeto, sendo as placas interligadas ponto-a-ponto sem a utilizaçao de transceivers analógicos. / This work presents the implementation of a network Ethernet 10/100Mbps core with interfaces to Avalon bus for using with the Nios II processor from Altera. The Ethernet technology was implemented in reconfigurable computing and was based in the OpenCores MAC 10/100 available on Internet. The project was developed for embedded systems applications, more specifically for a mobile robot in development at Reconfigurable Computing Laboratory from ICMC/USP. The core was incorporated to SoPC Builder tool’s library from Altera, aiming to facilitate the integration with others projects. To development and system tests were used Quartus II and ModelSim, and two Nios Development kit Statix Edition for project validation. The boards were linked peer-to-peer, without use analog transceivers.

O presente trabalho apresenta a implementação de um core de rede Ethernet 10/100Mbps com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. A tecnologia Ethernet foi implementada em computação reconfigurável e utilizou-se como base um módulo disponível na Internet denominado OpenCores MAC 10/100. O projeto foi desenvolvido para ser aplicado em sistemas embarcados, mais especificamente para o uso em um robô móvel em desenvolvimento no Laboratório de Computação Reconfigurável do ICMC/USP. O core foi incorporado à biblioteca da ferramenta SoPC Builder da Altera, visando uma fácil integração do mesmo em outros projetos. Foram utilizadas as ferramentas Quartus II e ModelSim para o desenvolvimento e testes do sistema, além de dois kits Nios versão Stratix para a validação do projeto, sendo as placas interligadas ponto-a-ponto sem a utilizaçao de transceivers analógicos. / This work presents the implementation of a network Ethernet 10/100Mbps core with interfaces to Avalon bus for using with the Nios II processor from Altera. The Ethernet technology was implemented in reconfigurable computing and was based in the OpenCores MAC 10/100 available on Internet. The project was developed for embedded systems applications, more specifically for a mobile robot in development at Reconfigurable Computing Laboratory from ICMC/USP. The core was incorporated to SoPC Builder tool’s library from Altera, aiming to facilitate the integration with others projects. To development and system tests were used Quartus II and ModelSim, and two Nios Development kit Statix Edition for project validation. The boards were linked peer-to-peer, without use analog transceivers.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / An integrated design, Test and Evaluation (T&E) system for GPS receiver is proposed in the paper, which can perform T&E early in R&D cycle, and combine new designs into a conceptual GPS receiver directly. The flowchart of its development mode is given. The architectures of the system, especially of the signal-computing software are described with frame diagrams. The mathematical models of three reference points are derived, with the impact of oscillator errors modeled. Future plans and further developments are also discussed.

<p>The thesis project consists on developing an interface for a Nios II processor integrated in a board of Altera (UP3- 2C35F672C6 Cyclone II).</p><p>The main goal is show how the Nios II processor can interact with the other components of the board.The Quartus II software has been used to create to vhdl code of the interfaces, compile it and download it into the board. The Nios II IDE tool is used to build the C/C++ files and download them into the processor.</p><p>It has been prepared an application for the audio codec integrated in the board (Wolfson WM8731 24-bit sigma-delta audio CODEC). The line input of the audio codec receives an analog signal from a laptop, this signal is managed by the control interface of the audio codec. The converters ADCs and DACs are stereo 24-bit sigma delta and they are used with oversampling digital interpolation and decimation filters.</p><p>The digital interface of the audio codec sends the digital signal to the Nios II processor and receives the data from the processor. After building the interfaces for the audio codec and the processor, it has been prepared an application in C++ language for the processor that modifies the volume of the signal.</p><p>The signal come back to the audio codec and it is possible to check the results with headphones or speakers at the line output of the audio codec.</p>

Cardiologists can gain useful insight into a patient's condition when they are able to correlate the patent's symptoms and activities. For this purpose, a Holter Monitor is often used - a portable electrocardiogram (ECG) recorder worn by the patient for a period of 24-72 hours. Preferably, the monitor is not cumbersome to the patient and thus it should be designed to be as small and light as possible; however, the storage requirements for such a long signal are very large and can significantly increase the recorder's size and cost, and so signal compression is often employed. At the same time, the decompressed signal must contain enough detail for the cardiologist to be able to identify irregularities. "Lossy" compressors may obscure such details, where a "lossless" compressor preserves the signal exactly as captured.<p>The purpose of this thesis is to develop a platform upon which a Holter Monitor can be built, including a hardware-assisted lossless compression method in order to avoid the signal quality penalties of a lossy algorithm. <p>The objective of this thesis is to develop and implement a low-complexity lossless ECG encoding algorithm capable of at least a 2:1 compression ratio in an embedded system for use in a Holter Monitor. <p>Different lossless compression techniques were evaluated in terms of coding efficiency as well as suitability for ECG waveform application, random access within the signal and complexity of the decoding operation. For the reduction of the physical circuit size, a System On a Programmable Chip (SOPC) design was utilized. <p>A coder based on a library of linear predictors and Rice coding was chosen and found to give a compression ratio of at least 2:1 and as high as 3:1 on real-world signals tested while having a low decoder complexity and fast random access to arbitrary parts of the signal. In the hardware-assisted implementation, the speed of encoding was a factor of between four and five faster than a software encoder running on the same CPU while allowing the CPU to perform other tasks during the encoding process.

Rapid progress in the area of Field-Programmable Gate Arrays (FPGAs) has led to the availability of softcore processors that are simple to use, and can enable the development of a fully working system in minutes. This has lead to the enormous popularity of System-On-Programmable-Chip (SOPC) computing platforms. These softcore processors, while relatively simple compared to their leading-edge hardcore counterparts, are often designed with a number of advanced performance-enhancing features, such as instruction and data caches. Moreover, they are designed to be used in a uniprocessor or uncoupled multiprocessor architecture, and not in a tightly-coupled multiprocessing architecture. As a result, traditional cache-coherency protocols are not suitable for use with such systems. This thesis describes a system for enforcing cache coherency on symmetric multiprocessing (SMP) systems using softcore processors. A hybrid protocol that incorporates hardware and software to enforce cache coherency is presented.