Orientador: José Alexandre Diniz / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-18T16:42:08Z (GMT). No. of bitstreams: 1 Lima_LucasPetersenBarbosa_M.pdf: 10518299 bytes, checksum: abe557fa5f682bd296c9fb416948d523 (MD5) Previous issue date: 2011 / Resumo: Filmes de nitreto de titânio (TiN) e nitreto de tântalo (TaN) foram depositados sobre substratos de Si (100) utilizando um sistema de sputtering reativo, com diferentes fluxos de N2 (10-80 sccm) e potência (500-1500W), em ambiente de N2/Ar. Foram analisadas as influências da mistura gasosa N2/Ar e potência nas propriedades estruturais e elétricas dos filmes de TiN e TaN, utilizando as técnicas de perfilometria, microscopia de força atômica, 4 pontas, espectroscopia Raman, difração de raios-x e espectroscopia de fotoelétron. As análises físicas e elétricas dos filmes de TiN e TaN demonstram que os filmes são policristalinos, com as orientações preferenciais (311)-( 111) e (200)-( 111), respectivamente. Os valores das taxas de deposições, resistividades elétricas e tamanho de grão para os filmes de TiN e TaN estão entre 4 e 78 nm/min, 150 e 7500 ??.cm e 0,001 e 0,027 ?m2, respectivamente. Foram fabricados capacitores MOS e diodos Schottky com eletrodos superiores de TiN e TaN com dielétricos de SiOxNy ou SiO2, e extraídas curvas CV e IV destes dispositivos, para extração de parâmetros como tensão de flatband (VFB), densidade de carga efetiva (Q0/q) e função trabalho do eletrodo superior (WF). As curvas CV dos capacitores MOS com dielétrico de SiOxNy e eletrodo superior de TiN apresentaram valores extraídos de Q0/q, VFB e WF de 1010 cm2, 0,29 V e 4,65 eV, respectivamente, que são compatíveis com a tecnologia CMOS. As curvas CV dos capacitores MOS com dielétrico de SiOxNy e eletrodo superior de TaN apresentaram valores extraídos de Q0/q, VFB e WF de 1010 cm2, 1,36 V e 3,81 eV, respectivamente, que não são compatíveis com a tecnologia CMOS. As curvas CV dos capacitores MOS com dielétrico de SiO2 e eletrodo superior de TiN apresentaram valores extraídos de Q0/q, VFB e WF de 1010 e 1012 cm2, de 0,12 V e 0,36 V, e, 4,15 eV e 4,43 eV, respectivamente, que são compatíveis com a tecnologia CMOS. As curvas CV dos capacitores MOS com dielétrico de SiO2 e eletrodo superior de TaN apresentaram valores extraídos de Q0/q, VFB e WF de 1010 e 1012 cm2, 0,29 V e 0,20 V, e, 4,41 eV e 4,44 eV, respectivamente, que são compatíveis com a tecnologia CMOS. Estes resultados indicam que os filmes de TiN e TaN são compatíveis para serem utilizados em dispositivos da tecnologia MOS / Abstract: Tantalum nitride (TaN) and titanium nitride (TiN) films have been obtained by DC sputtering, using different nitrogen flow (10 - 80 sccm) and power (500 - 1500 W), in a nitrogen (N2)/argon (Ar) ambient on Si (100) substrates. The N2/Ar ratio in gas mixture and power effects on structural and electrical properties of TaN and TiN films were investigated by scan profiler (film thickness and deposition rate), atomic force microscopy (rms roughness and grain size), fourprobe technique (electrical resistivity), Raman spectroscopy, x-ray diffraction (crystal orientation) and X-ray photoelectron spectroscopy (film composition). The physical and structural analyses of TiN and TaN films show that TiN and TaN films were polycrystalline, with (311)-( 111) and (200)-( 111) preferred orientation, respectively. The deposition rates, electrical resistivities and grain size values of TiN and TaN films were between 4 and 78 nm/min, 150 and 7500 ??.cm and 0,001-0,027 ?m2, respectively. MOS capacitors and Schottky diodes were fabricated with TiN and TaN as upper electrodes and dielectrics with SiOxNy or SiO2. CV and IV measurements were carried out on these devices and flatband voltage (VFB), effective charge density (Q0/q) and metal gate work function (WF) were extracted from these measurements. The extracted values of Q0/q, VFB e WF 1010 cm2, 0,29 V e 4,65 eV, and these values were extracted from CV curves of MOS capacitors with TiN as gate electrode and SiOxNy as gate dielectric. The extracted values of Q0/q, VFB e WF 1010 cm2, 1,36 V e 3,81 eV, and these values were extracted from CV curves of MOS capacitors with TiN as gate electrode and SiOxNy as gate dielectric. The extracted values of Q0/q, VFB and WF were about 1010 and 1012 cm2, 0,12 V and 0,36V, and 4,15 eV and 4,43 eV, and these values were extracted from CV curves of MOS capacitors with TiN as gate electrode and SiO2 as gate dielectric. The extracted values of Q0/q, VFB and WF were about 1010 and 1012 cm2, 0,29 V and 0,20V, and 4,41 eV and 4,44 eV, and these values were extracted from CV curves of MOS capacitors with TaN as gate electrode and SiO2 as gate dielectric. These extracted values for VFB and WF indicates that the TiN and TaN films are suitable for MOS technology / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

abstract: Silicon photonic technology continues to dominate the solar industry driven by steady improvement in device and module efficiencies. Currently, the world record conversion efficiency (~26.6%) for single junction silicon solar cell technologies is held by silicon heterojunction (SHJ) solar cells based on hydrogenated amorphous silicon (a-Si:H) and crystalline silicon (c-Si). These solar cells utilize the concept of carrier selective contacts to improve device efficiencies. A carrier selective contact is designed to optimize the collection of majority carriers while blocking the collection of minority carriers. In the case of SHJ cells, a thin intrinsic a-Si:H layer provides crucial passivation between doped a-Si:H and the c-Si absorber that is required to create a high efficiency cell. There has been much debate regarding the role of the intrinsic a-Si:H passivation layer on the transport of photogenerated carriers, and its role in optimizing device performance. In this work, a multiscale model is presented which utilizes different simulation methodologies to study interfacial transport across the intrinsic a-Si:H/c-Si heterointerface and through the a-Si:H passivation layer. In particular, an ensemble Monte Carlo simulator was developed to study high field behavior of photogenerated carriers at the intrinsic a-Si:H/c-Si heterointerface, a kinetic Monte Carlo program was used to study transport of photogenerated carriers across the intrinsic a-Si:H passivation layer, and a drift-diffusion model was developed to model the behavior in the quasi-neutral regions of the solar cell. This work reports de-coupled and self-consistent simulations to fully understand the role and effect of transport across the a-Si:H passivation layer in silicon heterojunction solar cells, and relates this to overall solar cell device performance. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2019

No description available.

Gallium Oxide (Ga2O3) is an ultra-wide bandgap semiconductor with a bandgap of 4.5–4.9 eV, which is larger than that of Silicon (Si), Silicon Carbide (SiC), and Gallium Nitride (GaN). A benefit of this ultra-wide bandgap is the high-temperature stability due to the low intrinsic carrier concentration. Another benefit is the high critical electric field (Ec), which is estimated to be from 6 MV/cm to 8 MV/cm in Ga2O3. This allows for a superior Baliga's figure of merit (BFOM) of unipolar Ga2O3 power devices, i.e., they potentially can achieve a smaller specific on-resistance (RON,SP) as compared to the Si, SiC, and GaN devices with the same breakdown voltage (BV). The above prospects make Ga2O3 devices the promising candidates for next-generation power electronics. This dissertation explores the design, fabrication, characterization, and packaging of vertical β-Ga2O3 Schottky barrier diodes (SBDs) and P-N diodes. The power SBDs allow for a small forward voltage and a fast switching speed; thus, it is ubiquitously utilized in power electronics systems. Meanwhile, the Ga2O3 power P-N diodes have the benefit of smaller leakage current, and the diode structure could be a building block for many advanced diodes and transistors. Hence, the study of Ga2O3 Schottky and P-N diodes is expected to provide the foundation for developing a series of Ga2O3 power devices. Firstly, vertical Ga2O3 Schottky and P-N diodes with a novel edge termination (ET), the multi-layer Nickel Oxide (NiO) junction termination extension (JTE), are fabricated on Ga2O3 substrates. This multi-JTE NiO structure decreases the peak electric field (Epeak) at the triple point of device edge when the Ga2O3 diodes are reversely biased. For SBDs, BV reach 2.5 kV, the 1-D junction field reaches 3.08 MV/cm, and the BFOM exceeds 1 GW/cm2. For P-N diodes, BV reaches 3.3 kV, the junction field reaches 4.2 MV/cm, and the BFOM reaches 2.6 GW/cm2. These results are among the highest in Ga2O3 power devices and are comparable to the state-of-the-art vertical GaN Schottky and P-N diodes. Notably, all these diodes are small-area devices. Secondly, large-area (3 mm×3 mm anode size) Ga2O3 Schottky and P-N diodes with high current capability are fabricated to explore the packaging, thermal management, and switching characteristics of Ga2O3 diodes. The same ET is applied for the large-area P-N diode. The fabricated large-area P-N diodes have a turn-on voltage of 2 V, a differential on-resistance (Ron) of 0.2 Ω, and they can reach at least 15 A when measured in the pulse mode. The BV of large-area Ga2O3 P-N diodes varies due to the fabrication non-uniformity, but the best device achieves a BV of 1.6 kV, standing among the highest values reported for large-area Ga2O3 diodes. Also, the large-area Ga2O3 SBDs with similar current rating but with a FP ET are fabricated mainly for the packaging and thermal management studies. Thirdly, medium-area Ga2O3 P-N diodes with a current over 1 A and a higher yield of BV are fabricated to evaluate the JTE's capacitance and switching characteristics. The JTE accounts for only ~11% of the junction capacitance of this 1 A diode, and the percentage is expected to be even smaller for higher-current diodes. The turn-on/off speed and reverse recovery time of the diode are comparable to commercial SiC Schottky barrier diodes under the on-wafer switching test. These results show the viability of NiO JTE for enabling a fast switching speed in high-voltage Ga2O3 power devices. Fourthly, the fabricated large-area Ga2O3 diodes are packaged using silver sintering as the die attach. The sintered silver joint has higher thermal conductivity (kT) and better reliability as compared to the solder joint. Due to the low kT of Ga2O3 material, junction-side-cooled (JSC) packaging configuration is necessary for Ga2O3 devices. For the packaged device, its junction-to-case thermal resistance (RθJC) is measured in the bottom-side-cooled (BSC) and junction-side-cooled (JSC) configuration by the transient dual interface method according to the JEDEC 51-14 standard. The RθJC of the junction- and bottom-cooled Ga2O3 SBD is measured to be 0.5 K/W and 1.43 K/W, respectively. The former RθJC is lower than that of similarly-rated commercial SiC SBDs. This manifests the significance of JSC packaging for the thermal management of Ga2O3 devices. Fifthly, to evaluate the electrothermal robustness of the packaged Ga2O3 devices, the surge current capability of JSC packaged Ga2O3 SBDs are measured. The Ga2O3 SBDs with proper packaging show high surge current capabilities. The double-side-cooled (DSC) large-area Ga2O3 SBDs can sustain a peak surge current over 60 A, with a ratio between the peak surge current and the rated current superior to that of similarly-rated commercial SiC SBDs. These results show the excellent ruggedness of Ga2O3 power devices. Finally, a Ga2O3 integrated diode module consisting of four single-diode sub-modules is designed and fabricated. For many power electronics applications, high current is desired; however, for emerging semiconductors, the current upscaling is difficult by directly increasing the device area because of the limitation of heat extraction capability and the limited material/processing yield. Here we explore the paralleling of multiple Ga2O3 P-N diodes to increase the current level. For each sub-module, the JSC packaging structure is used for heat extraction, and a metal post is sintered to the anode for electric field (E-field) management. RθJC is measured to be 1 W/K for each sub-module. On-board double-pulsed test is performed for both the sub-module and the full module. The sub-module and full module demonstrate 400 V, 10 A and 150 V, 70 A switching capabilities, respectively. This is the first demonstration of Ga2O3 power module and shows a promising approach to upscale of the power level of Ga2O3 power electronics. In addition to Ga2O3 device study, a research is conducted to explore the chip size (Achip) minimization for wide-bandgap (WBG) and ultra-wide bandgap (UWBG) power devices. Achip optimization is particularly critical for WBG and UWBG power devices and modules due to the high material cost. This work presents a new, holistic, electrothermal approach to optimize Achip for a given set of target specifications including BV, conduction current (I0), and switching frequency (f). The conduction and switching losses of the device are considered, as well as the heat dissipation in the chip and its package. For a given BV and I0, the optimal Achip, Wdr, and Ndr show strong dependence on f and thermal management. Our approach offers more accurate cost analysis and design guidelines for power modules. In summary, this dissertation covers the design, fabrication, characterization, and packaging of Ga2O3 Schottky and P-N diodes, with the aim to advance Ga2O3 devices to power electronics applications. This dissertation addresses many knowledge gaps on Ga2O3 devices, including the voltage upscaling (ET), current upscaling (large-area device fabrication, packaging, and thermal management), and their concurrence (module demonstration), as well as the circuit-level switching characterizations. / Doctor of Philosophy / Power electronics is the processing of electric energy using solid-state electronics. It is ubiquitously used in consumer electronics, data centers, electric vehicles, electricity grids, and renewable energy systems. Advanced power device technologies are paramount to improving the performance of power electronic systems. Power device design centers on the concurrent realization of low on-resistance (RON), high breakdown voltage (BV), and small turn-on/turn-off power losses. A key driver for advancement of power devices is the semiconductor material. Over the last decade, power devices based on wide-bandgap semiconductors like SiC and GaN have enabled tremendous performance advancements in power electronic systems. On the horizon, Ga2O3 is an emerging semiconductor with an ultra-wide bandgap (UWBG) of 4.5–4.9 eV, which is higher than that of Si, SiC, and GaN. Benefitted from this larger bandgap, the theoretical performance of Ga2O3 power devices is superior to the Si, SiC, and GaN counterparts. Hence, Ga2O3 devices are regarded as the promising candidates for next-generation power electronics. The power diode is an important component in power circuits, and the diode structure is usually a building block for power transistors. Small-area (0.1 A current level) Ga2O3 Schottky barrier diodes (SBDs) and P-N diodes are first designed and fabricated with a novel ET, the NiO JTE, reaching a high BV from 2.5 to 3.5 kV and junction E-field up to 4.2 MV/cm. Subsequently, large-area (>15 A current level) Ga2O3 diodes are fabricated with the same ET, achieving a BV of 1.6 kV, which is among the highest BV demonstrated in large-area Ga2O3 devices. In addition, on-wafer switching tests are performed on the medium-area (1 A current level) Ga2O3 P-N diodes, and their turn-on/off speed and reverse recovery time are comparable to commercial SiC Schottky barrier diodes. In addition to voltage upscaling, current upscaling is also a key challenge for Ga2O3 power devices. To overcome the low thermal conductivity (kT) of Ga2O3, junction side cooling (JSC) packaging is used to increase the heat extraction capability of Ga2O3 diode, enabling the demonstration of a junction-to-case thermal resistance comparable to that of similarly-rated, commercial SiC diode. Benefitted from this enhanced heat extraction, the packaged Ga2O3 diodes show an excellent surge current robustness. Finally, a Ga2O3 integrated diode module consisting of four single-diode sub-modules is designed, fabricated, and tested in the on-board switching circuits up to 70 A and 400 V. This is the first demonstration of a Ga2O3 power module. In summary, this dissertation covers the design, fabrication, characterization, and packaging of Ga2O3 power diodes with the aim to advance Ga2O3 devices to power electronics applications. This dissertation addresses many knowledge gaps on the voltage upscaling, current upscaling, and the circuit-level switching characteristics of Ga2O3 power devices and modules and thus pave the road for their power electronics applications.

The aggressive reduction of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has resulted in an exponential increase in computing power. Stemming from increases in device density and substantial progress in materials science and transistor design, the integrated circuit has seen continual performance improvements and simultaneous reductions in operating power (VDD). Nevertheless, existing Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are rapidly approaching the physical limits of their scaling potential. New material innovations, such as binary group IV or ternary III-V compound semiconductors, and novel device architectures, such as the tunnel field-effect transistor (TFET), are projected to continue transistor miniaturization beyond the Si CMOS era. Unlike conventional MOSFET technology, TFETs operate on the band-to-band tunneling injection of carriers from source to channel, thereby resulting in steep switching characteristics. Furthermore, narrow bandgap semiconductors, such as germanium (Ge) and InxGa1-xAs, enhance the ON-state current and improve the switching behavior of TFET devices, thus making these materials attractive candidates for further study. Moreover, epitaxial growth of Ge on InxGa1-xAs results in tensile stress (ε) within the Ge thin-film, thereby giving device engineers the ability to tune its material properties (e.g., mobility, bandgap) via strain engineering and in so doing enhance device performance. For these reasons, this research systematically investigates the material, optical, electronic transport, and heterointerfacial properties of ε-Ge/InxGa1-xAs heterostructures grown on GaAs and Si substrates. Additionally, the influence of strain on MOS interfaces with Ge is examined, with specific application toward low-defect density ε-Ge MOS device design. Finally, vertical ε-Ge/InxGa1-xAs tunneling junctions are fabricated and characterized for the first time, demonstrating their viability for the continued development of next-generation low-power nanoelectronic devices utilizing the Ge/InxGa1-xAs material system. / Doctor of Philosophy / The aggressive scaling of transistor size in silicon-based complimentary metal-oxide-semiconductor technology has resulted in an exponential increase in integrated circuit (IC) computing power. Simultaneously, advances in materials science, transistor design, IC architecture, and microelectronics fabrication technologies have resulted in reduced IC operating power requirements. As a consequence, state-of-the-art microelectronic devices have computational capabilities exceeding those of the earliest super computers at a fraction of the demand in energy. Moreover, the low-cost, high-volume manufacturing of these microelectronic devices has resulted in their nigh-ubiquitous proliferation throughout all aspects of modern life. From social engagement to supply chain logistics, a vast web of interconnected microelectronic devices (i.e., the "Internet of Things") forms the information technology bedrock upon which 21st century society has been built. Hence, as progress in microelectronics and related fields continues to evolve, so too does their impact on an increasingly dependent world. Moore's Law, or the doubling of IC transistor density every two years, is the colloquialism used to describe the rapid advancement of the microelectronics industry over the past five decades. As mentioned earlier, parallel improvements in semiconductor technologies have spearheaded great technological change. Nevertheless, Moore's Law is rapidly approaching the physical limits of transistor scaling. Consequently, in order to continue improving IC (and therefore microelectronic device) performance, new innovations in materials and fabrication science, and transistor and IC designs are required. To that end, this research systematically investigates the material, optical, and electrical properties of novel semiconductor material systems combining elemental (e.g., Germanium) and compound (e.g., Gallium Arsenide) semiconductors. Additionally, alternative transistor design concepts are explored that leverage the unique properties of the aforementioned materials, with specific application to low-power microelectronics. Therefore, through a holistic approach towards semiconductor materials, devices, and circuit co-design, this work demonstrates, for the first time, novel transistor architectures suitable for the continued development of next-generation low-power, high-performance microelectronic devices.

Significant progress in reducing the growth temperature of the SiC epitaxial growth became possible in the previous work by using new chloro-carbon epitaxial growth method. However, it was established that even in the new process, homogenous nucleation of Si in the gas phase limited the growth rate. In the present work, new chlorinated silicon precursor SiCl4 was investigated as a replacement for the traditional silicon precursor SiH4 during the low-temperature chlorocarbon epitaxial growth. The new process completely eliminated the homogenous nucleation in the gas phase. Growth rate of 5-6 μm/h was achieved at 1300°C compared to less than 3 μm/h in the SiH4-based growth. The growth dependence on the C/Si ratio revealed that the transition from the C-supply-limited to the Si-supply-limited growth mode takes place at the value of the C/Si ratio much higher than unity, suggesting that certain carbon-containing species are favorably excluded from the surface reactions in the new process. Morphology degradation mechanisms, which are unique for the lowtemperature growth, were observed outside the established process window. Prior to this work, it remained unclear if CH3Cl simply served as a source of Cl to suppress homogeneous nucleation in the gas phase, or if it brought some other unknown improvements. In this work true benefits of CH3Cl in providing unique improvement mechanisms have been revealed. It was established that CH3Cl provided a much wider process window compared to C3H8. In contrast, even a very significant supply of extra Cl from a chlorinated silicon precursor or from HCl during the C3H8-based growth could not provide a similar benefit. The combination of the chloro-carbon and the chloro-silane precursors was also investigated at conventional growth temperature. High-quality thick epitaxial layers, with the growth rate up to 100μm/h were obtained, and the factors influencing the growth rate and morphology were investigated. Extensive optical and electrical characterization of the low-temperature and the regular-temperature epitaxial layers was conducted. The device-quality of the lowtemperature chloro-carbon epilayers was validated for the first time since the development of the chloro-carbon epitaxial process in the year 2005 by fabricating simple Schottky diodes and investigating their electrical characteristics.

No description available.

The MOS-gated thyristors (MGT) refer to the class of power devices that combine the ease of a MOS gate control with the superior current carrying capability of a thyristor structure for high-power applications. The MOS-controlled thyristor (MCT) is a typical MGT device. A comprehensive investigation of the reverse-biased safe operating area (RBSOA) characteristics of the MCT has been undertaken. The electrical failure mechanisms of the MCT are discussed, and the relationship between the dynamic avalanche limited RBSOA boundary of the MCT and the lower open-base transistor is identified. An analytical model based on the dynamic current gain concept is proposed to characterize the open-base transistor. For the first time, a RBSOA characteristic equation is developed for the MCT and a unified view of the RBSOA characteristics of the MCT is presented. The fundamental characteristics of the MCT are compared to those of the insulated gate bipolar transistor (IGBT) at two levels: unit-cell and multi-cell. The investigation of the unit-cell level focuses on the tradeoff between the on-state voltage drop, the turn-off loss, and the RBSOA characteristic. The investigation of the multi-cell level reveals the fundamental difference between the MCT and the IGBT in handling the non-uniform turn-off caused by the internal propagation gate delay of a large-area device. Lack of current saturation capability is identified as the main reason for the severe degradation of the turn-off capability of a large-area multi-cell MCT. The current saturation and controlled turn-on capabilities can be realized in the MGT devices with dual operation modes. For the first time, a dual operation mode MCT developed with superior current saturation capability is used to demonstrate how the dual operation device can be beneficial in the switching circuit application. The maximum controllable current density (Jmcc) is the most important characteristic of the dual operation mode MGT devices. A first-order analytic model is developed to characterize the Jmcc of the dual operation mode MGT structures compatible with the IGBT fabrication process. A new device structure with improved Jmcc characteristics is proposed and verified by both simulation and experimental results. The dissertation also carries out a comprehensive investigation of the development of power diodes. A new power diode, called the Trench Bipolar Junction Diode (TBJD), which has superior dynamic characteristics over the conventional P-i-N diode, is proposed. The TBJD controls the anode injection efficiency of the diode by the action of a reverse active transistor structure integrated into its anode junction. The reverse active transistor helps tailor an optimized on-state carrier profile to improve the diode switching characteristics. A novel self-aligned process is developed to fabricate the TBJD. Experimental characterization of the fabricated TBJD devices shows that the TBJD achieves superior dynamic characteristics without sacrificing the on-state voltage drop and the leakage current characteristics. / Ph. D.

Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing total power consumption and thus, necessitates supply voltage scaling in order to maintain low-power device operation. However, with increased supply voltage scaling, transistor drive current is significantly degraded due to the low carrier mobility of Si. To overcome the key challenges of device and voltage scaling required for low-power electronic operation without the degradation of transistor drive current requires the adoption of narrow bandgap channel materials with superior transport properties. However, the use of such materials as bulk substrates remains cost-prohibitive. Thus, another key challenge lies in the heterogeneous integration of high-mobility channel materials on affordable, established Si platform. Germanium (Ge) is an attractive candidate for next-generation low-power devices owing to its high electron and high hole mobility. Recently, AlAs/GaAs epilayers were demonstrated as a potential buffer platform for next-generation Ge-based electronics integrated on Si substrate. This research systematically investigates the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C's) fabricated on the aforementioned stack. Further passivation techniques and interface engineering is then pursued on MOS-C's fabricated from (100) and (110) crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks, balancing out effective oxide thickness (EOT) and reduction of oxide and interfacial traps in order to ensure a pristine interfacial quality for high-performance electronic applications. Further, work function tuning is demonstrated for the first time on the different crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks using two different gate metals, demonstrating the tunability of threshold voltage, VTH, required for transistor applications. The research demonstrates the feasibility of future high-mobility channel material integration on Si via large bandgap buffer architectures for high-speed, low-power, high-performance CMOS logic applications. / Master of Science

Developing high efficiency solar cells for lower manufacturing costs has been a key objective for photovoltaic researchers to drive down the levelized cost of energy for solar power. In this pursuit, III-V compound semiconductor based solar cells have steadily shown performance improvement at approximately 1% (absolute) increase per year, with a recent record efficiency of 46% under concentrator and 32% under AM0. However, the expensive cost has made it challenging for III-V solar cells to compete with the mainstream Silicon (Si) technology. Novel approaches to lower down the cost per watt for III-V solar cells will position them to be among the key contenders in the renewable energy sector. Integration of such high-efficiency III-V multijunction solar cells on significantly cheaper and large area Si substrate has the potential to address the future LCOE roadmaps by unifying the high-efficiency merits of III-V materials with low-cost and abundance of Si. However, the 4% lattice mismatch, thermal mismatch, polar on non-polar epitaxy makes the direct growth of GaAs on Si challenging, rendering the metamorphic cell sensitive to dislocations. The focus of this dissertation is to investigate heterogeneously integrated 1J GaAs solar cells on Si substrate using germanium (Ge) as an intermediate buffer layer that will address mitigation of defects and dislocations between GaAs active cell structure and Ge “virtual” substrate on Si. The all-epitaxial molecular beam epitaxy (MBE)-grown thin (<1 μm) hybrid GaAs/Ge “virtual” buffer approach provided 1J GaAs cell efficiency of ~10% on Si, as compared with cell structures with thick 3 μm GaAs buffers. Solar cell results were further corroborated with material analysis to provide a clear path for the reduction of performance limiting dislocations. The thin “Ge-on-Si” virtual buffer was then investigated comprehensively to understand the impact of the heterostructure on device performance. The growth, structural, morphological, and electrical transport properties of epitaxial thin-film Ge, grown by solid source MBE on Si using a two-step growth process, were investigated. High-resolution x-ray diffraction analysis demonstrated ~0.10% tensile strained Ge epilayer, owing to the thermal expansion coefficient mismatch between Ge and Si, and negligible epilayer lattice tilt due to misfit dislocations at the Ge/Si heterointerface. Micro-Raman spectroscopic analysis further corroborated the strain-state of the Ge thin-film on Si. Cross-sectional transmission electron microscopy revealed the formation of a 90° Lomer dislocation network at the Ge/Si heterointerface, suggesting the rapid and complete relaxation of the Ge epilayer during growth. Atomic force micrographs exhibited smooth surface morphologies with surface roughness < 2 nm. Hall mobility measurements, performed within a temperature range of 77 K to 315 K, and the modelling thereof indicated that ionized impurity scattering limited carrier mobility in the thin Ge epilayer. Additionally, capacitance- and conductance-voltage measurements were performed after fabricating the metal-oxide-semiconductor capacitors (MOS-Cs) in order to determine the effect of epilayer dislocation density on interfacial defect states (Dit), bulk trap density, and the energy distribution of Dit as a function of temperature for electronic device applications. Deep level transient spectroscopy was used to identify the location (within the Ge bandgap) of electrically active trap levels; however, no significant trap levels were detected. Finally, the extracted Dit values were benchmarked against previously reported Dit data for Ge MOS devices, as a function of threading dislocation density within the Ge layer. The results obtained in this work were found to be comparable with other Ge MOS devices integrated on Si via alternative buffer schemes. The understanding gained from this comprehensive study of Ge-on-Si will help optimize the 1J GaAs on Si via thin Ge buffer approach, to enable a future of high efficiency low cost solar cells for terrestrial applications. / Master of Science / The global energy landscape is projected to change remarkably in the coming decades with dwindling carbon based resource reserves and escalating energy demands, necessitating large-scale adoption of cleaner alternatives, such as solar energy. However, for widespread commercial and domestic adoption of photovoltaics, the cost of solar generated electricity must become competitive with non-renewable resources such as oil or coal. Thus, achieving high efficiency solar cells and driving down cell costs are key research objectives of the photovoltaic (PV) community in order to become more self-sufficient in the energy sector. In this pursuit, III-V compound semiconductor-based solar cells have steadily outperformed all other PV technologies, but cost-prohibitive for terrestrial deployment. Si is the undisputed standard in the PV industry; thus, to make a significant step forward in the pursuit of high efficiency solar cells, a promising approach will be to integrate the superior properties of compound semiconductors with the mature technology of Si. This research systematically investigates the integration of high efficiency III-V cells with low cost, abundant Si substrates via a germanium (Ge) layer to unify the performance merits of III-V cells with the cost benefits and superior mechanical and thermal properties of Si. Concurrently, Ge has also emerged as a strong candidate to boost transistor performance at low operating voltages, primarily owing to its superior carrier mobility and ease of integration into mainstream Si process flow. This research further delves into the structural and electrical properties of the Ge on Si structure. Overall, this research demonstrates the feasibility of the use of Ge directly integrated on Si for high efficiency solar cells and low-power electronic devices.