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This Master thesis deals with modification of lead battery charger connection. In particular, changes are made to the control board. The theoretical part describes the principle of charging lead batteries and the description of the basic types of switching power supplies. Furthermore, the dimensioning of important components in the circuit together with the optimization of the switching frequency and the parameters of the high-frequency transformer are also presented. At the end of the thesis is the procedure of assembling the whole charger.

In the semiconductor industry the reliability of devices is of paramount importance. Therefore, after removing the defective ones, one wants to detect irregularities in measurement data because corresponding devices have a higher risk of failure early in the product lifetime. The paper presents a method to improve the detection of such suspicious devices where the screening is made on transformed measurement data. Thereby, e.g., dependencies between tests can be taken into account. Additionally, a new dimensionality reduction is performed within the transformation, so that the reduced and transformed data comprises only the informative content from the raw data. This simplifies the complexity of the subsequent screening steps. The new approach will be applied to semiconductor measurement data and it will be shown, by means of examples, how the screening can be improved.

The third quadrant (3rd-quad) conduction (or reverse conduction) of power transistors is critical for synchronous power converters. For power metal-oxide-semiconductor field-effect-transistors (MOSFETs), there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is well known that, for 1.2 kV silicon carbide (SiC) planar MOSFETs, the conduction loss in the 3rd-quad is reduced by turning on the MOS channel with a positive gate bias (VGS) and keeping the dead time as small as possible. Under this scenario, the current is conducted through both paths, allowing the device to take advantage of the zero 3rd-quad forward voltage drop (VF3rd) of the MOS channel path and the small differential resistance of the body diode path. However, in this thesis work, this popular belief is found to be invalid for power MOSFETs with higher voltage ratings (e.g., 3.3 kV and 10 kV), particularly at high temperatures and current levels. The aforementioned MOS channel and body diode paths compete in the device’s 3rd-quad conduction, and their competition is affected by VGS and device structure. This thesis work presents a comparative study on the 3rd-quad behavior of 1.2 kV to 10 kV SiC planar MOSFET through a combination of device characterization, TCAD simulation and analytical modeling. It is revealed that, once the MOS channel turns on, it changes the potential distribution within the device, which further makes the body diode turn on at a source-to-drain voltage (VSD) much higher than the built-in potential of the pn junction. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on over the entire practical VSD range. As a result, the positive VGS leads to a completely unipolar conduction via the MOS channel, which could induce a higher VF3rd than the bipolar body diode at high temperatures. Circuit test is performed, which validates that a negative VGS control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures in 10 kV SiC planar MOSFET. The study is also extended to the trench MOSFET, another major structure of commercial SiC MOSFETs. Based on the revealed physics for planar MOSFETs, the optimal VGS control for the 3rd-quad conduction in different types of commercial trench MOSFETs is discussed, which provides insights for the design of high-voltage trench MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs. / M.S. / Recent years, the prosperity of power electronics applications such as electric vehicle and smart grid has led to a rapid increase in the adoption of wide bandgap (WBG) power devices. Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, capability of operation at high temperatures, and superior device robustness over other WBG power devices. In most power converters, power device is required to conduct current in its third quadrant (3rd-quad) (i.e., conduct reverse current) either for handling current during the dead time or acting as a commutation switch. In a SiC MOSFET, there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is widely accepted that by turning on the MOS channel with a positive gate-to-source bias (VGS), both paths are turned on in parallel such that the 3rd-quad conduction loss can be reduced. In this thesis work, it is shown that this long-held opinion does not hold for SiC MOSFETs with high voltage ratings (e.g., 3.3 kV and 10 kV). Through a combination of device characterization, TCAD simulation, and analytical modeling, this thesis work unveils the competing current sharing between the MOS channel and the body diode. Once the MOS channel turns on, it delays the turn-on of the body diode and suppresses the diode current. This effect is more pronounced in MOSFETs with higher voltage ratings. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on in the practical operation conditions. At high temperatures, as the bipolar diode path possesses the conductivity modulation, which can significantly lower the voltage drop and is absent in the MOS channel, it would be optimal to turn off the MOS channel. Circuit test is also performed to validate these device findings and evaluate their impact on device applications. Finally, the study is also extended to the commercial SiC trench MOSFET, the other mainstream type of SiC power MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs.

Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids. / Doctor of Philosophy / In recent years, many power electronics applications such as data centers and electric vehicles have witnessed a rapid increase in the adoption of wide bandgap (WBG) power devices. The Gallium Nitride (GaN) device is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, as well as the small gate charge that enables high frequency switching. For power devices, their robustness against overvoltage and overcurrent stresses is as important as their performance under normal operations. However, the new material, new device structure, and new device physics in GaN power devices brought up many open knowledge gaps in their robustness study, particularly under the dynamic operation in switching circuits. This dissertation presents the work in exploring the robustness of GaN power devices. Based on the device structure, the discussion is divided in two parts: The first half of the dissertation focuses on the overvoltage robustness of the lateral GaN High Electron Mobility Transistor (HEMT), the commercially available device covering 30 to 900 V voltage classes. A key feature of this device is the lack of p-n junction between source and drain, leading to an absence of avalanche capability. The study is conducted on mainstream, commercial p-gate GaN HEMTs, with a combination of circuit testing, microscale failure analysis, and physics-based device simulation. The main contribution is on three aspects: identifying the single-event and high-frequency repetitive overvoltage boundaries of GaN HEMT, unveiling the failure and degradation mechanisms under transient overvoltage conditions, and providing guidelines to GaN HEMT device users with proper robustness test methodology for device qualification and screening. The second half of the dissertation focuses on the robustness of vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercial GaN power device with the p-n junction implemented between the source and drain. The robustness tests follow the classic approaches deployed for Silicon power devices, where both the avalanche and short circuit capabilities are investigated. From the single-event and repetitive test results, the GaN JFET shows excellent avalanche robustness with a desirable failure-to-open-circuit behavior, as well as a critical avalanche energy (EAVA) of 10 J/cm2 that is higher than the Silicon metal-oxide-semiconductor field-effect transistor (MOSFET) and comparable to the Silicon Carbide MOSFET. For a 650-V rated GaN Fin-JFET, a record high 30.5 μs short circuit time is demonstrated under the hard-switching fault condition at 400 V input voltage. Overall, the results show great potential of GaN power devices for the power electronics applications that involve more stressful operation conditions for devices.

Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices. / Doctor of Philosophy / Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. Currently, GaN power devices performance is still far below its material limit due to several reasons: 1) To achieve normally-off operation, the carriers at gate region need to be fully depleted at zero bias. Due to a relatively limited depletion capability of the planar gate, the normally-off operation poses an upper limit on the channel carrier density, which increases the device on-resistance. 2) The electric field distribution is not uniform when the device is blocking off-state voltage, and the crowded electric field will cause the device premature breakdown. This work proposed to use multi-dimensional, p-n junction-based device structure to overcome the above challenges. The devices with diverse structures are fabricated, characterized, and compared with the commercially available devices. The multi-dimensional, junction-based gate structure provides strong electrostatic control to realize normally-off operation and allow for higher carrier concentration and lower on-resistance. The devices with multi-dimensional, junction-based drift region enables the uniform electric field distribution at the device off-state, allowing devices to block high voltage without compromising the on-state resistance. Examples of such devices investigated in this dissertation include the tri-gate junction transistors, reduced-surface-field (RESURF) diodes, and superjunction diodes. In summary, this work demonstrates the multi-dimensional, junction-based device structure to overcome the performance limitations of planar devices and fully exploit GaN's material benefits for power devices. The multi-dimensional, junction-based devices are experimentally fabricated and characterized, manifesting the superior performance over traditional GaN devices. This work will significantly boost the performance and application space of GaN power devices.

Controlled thin film etching is essential for future semiconductor devices, especially with complex high aspect ratio structures. Therefore, self-limiting atomic layer etching processes are of great interest to the semiconductor industry. In this work, a process for atomic layer etching of aluminum oxide (Al2O3) films using sequential and self-limiting thermal reactions with trimethylaluminum and hydrogen fluoride as reactants was demonstrated. The Al2O3 films were grown by atomic layer deposition using trimethylaluminum and water. The cycle-by-cycle etching was monitored throughout the entire atomic layer etching process time using in situ and in real-time spectroscopic ellipsometry. The studies revealed that the sequential surface reactions were self-limiting versus reactant exposure. Spectroscopic ellipsometry analysis also confirmed the linear removal of Al2O3. Various process pressures ranging from 50 to 200 Pa were employed for Al2O3 etching. The Al2O3 etch rates increased with process pressures: Al2O3 etch rates of 0.92, 1.14, 1.22, and 1.31 Å/cycle were obtained at 300 °C for process pressures of 50, 100, 150, and 200 Pa, respectively. The Al2O3 etch rates increased with the temperature from 0.55 Å/cycle at 250 °C to 1.38 Å/cycle at 350 °C. Furthermore, this paper examined the temperature dependence of the rivalry between the removal (Al2O3 etching) and growth (AlF3 deposition) processes using the reactants trimethylaluminum and hydrogen fluoride. The authors determined that 225 °C is the transition temperature between AlF3 atomic layer deposition and Al2O3 atomic layer etching. The high sensitivity of in vacuo x-ray photoelectron spectroscopy allowed the investigation of the interface reactions for a single etching pulse as well as the initial etch mechanism. The x-ray photoelectron spectroscopy measurements indicated that the fluorinated layer is not completely removed after each trimethylaluminum exposure. The Al2O3 atomic layer etching process mechanism may also be applicable to etch other materials such as HfO2.

This thesis investigates novel hole extraction interfaces and series interconnects for applications in organic photovoltaics, specifically in single junction solid-state dye-sensitized solar cells (DSSCs) and tandem DSSC/polymer bulk heterojunction solar cells. Improvements in hole extraction and device performance by using materials compatible with scalable deposition methods are presented, including tungsten- and molybdenum-disulphide (WS₂ and MoS₂), and p-type doped spiro-OMeTAD (2,2',7,7'-tetrakis-(N,N-di-p-methoxyphenylamine)9,9'-spirobifluorene) nanoparticle dispersions. WS₂ and MoS₂ hole extraction layers increase averaged short circuit currents by 20% and 16% respectively, and power conversion efficiencies by 19% and 14% respectively when compared with control devices. Similarly, doped spiro-OMeTAD nano-particle layers improved short circuit current densities by 32% and efficiencies by 9%. Tandem device interconnects using these novel hole extraction formats have been fabricated, but although devices did exhibit rectification, overall performance was poor. Possible reasons for their limited success have been analysed. Dye-sensitized solar mini-modules are also reported. In order to assure the scalability of DSSC technology, these larger area devices were constructed using doctor blade coating to deposit the hole transporter material. As well as achieving a respectable maximum power conversion efficiency of 2.6%, it has also been shown that the extent to which hole transporter infiltrates the mesoporous photoanode of these devices may be tuned by altering substrate temperature during deposition. It was found that an optimal coating temperature of 70 degrees C produced the best efficiency, with a corresponding pore-filling fraction of 41%.

This thesis studies lead suphide (PbS) colloidal quantum dots and their photovoltaic applications. Different sizes of PbS QDs were synthesised and characterised using absorption spectroscopy and transmission electron microscopes. PbS QD Schottky junction devices were fabricated with AM1.5 power conversion efficiency up to 1.8 %. The Schottky junction geometry limits the device performance. A semiconductor heterojunction using ZnO as an electron acceptor was built and the device efficiency increased to 3%. By studying the light absorption and charge extraction profile of the bilayer device, the absorber layer has a charge extraction dead zone which is beyond the reach of the built-in electric field. Therefore, strategies to create a QD bulk heterojunction were considered to address this issue by distributing the junction interface throughout the absorber layer. However, the charge separation mechanism of the QD heterojunction is not clearly understood: whether it operates as an excitonic or a depleted p-n junction, as the junction operating mechanism determines the scale of phase separation in the bulk morphology. This study shows a transitional behaviour of the PbS/ZnO heterojunction from excitonic to depletion by increasing the doping density of ZnO. To utilise the excitonic mechanism, a PbS/ZnO nanocrystal bulk heterojunction was created by blending the two nanocrystals in solution such that a large interface between the two materials could facilitate fast exciton dissociation. However, the devices show poor performance due to a coarse morphology and formation of germinate pairs. To create a bulk heterojunction where a built-in electric field could assist the charge separation, a TiO₂ porous structure with the pore size matching with the depletion width was fabricated and successfully in-filled by PbS QDs. The porous device produces 5.7% power conversion efficiency, among one of the highest in literature. The enhancement comes from increased light absorption and suppression of charge recombination.

This thesis is concerned with studying the fascinating quantum properties of real-world nanostructures embedded in a noisy condensed matter environment. The interaction with light is used for controlling and manipulating the quantum state of the systems considered here. In some instances, laser pulses also provide a way of actively probing and controlling environmental interactions. The first two research chapters assess two different ways of performing all-optical spin qubit gates in self-assembled quantum dots. The principal conclusion is that an `adiabatic' control technique holds the promise of achieving a high fidelity when all primary sources of decoherence are taken into account. In the next chapter, it is shown that an optically driven quantum dot exciton interacting with the phonons of the surrounding lattice acts as a heat pump. Further, a model is developed which predicts the temperature-dependent damping of Rabi oscillations caused by bulk phonons, finding an excellent agreement with experimental data. A different system is studied in the following chapter: two electron spin qubits with no direct interaction, yet both exchange-coupled to an optically active mediator spin. The results of this study show that these general assumptions are sufficient for generating controlled electron spin entanglement over a wide range of parameters, even in the presence of noise. Finally, the Radical Pair model of the avian compass is investigated in the light of recent experimental results, leading to the surprising prediction that the electron spin coherence time in this molecular system seems to approach the millisecond timescale.