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Titanium dioxide (TiO2) thin films have a long history in silicon photovoltaics (PV) as antireflection (AR) coatings due to their excellent optical properties and low deposition cost. This work explores several novel areas where TiO2 thin films could be use to enhance silicon (Si) solar cell performance while reducing device fabrication costs. Amorphous, anatase and rutile TiO2 thin films are deposited using ultrasonic spraydeposition (USD) and chemical vapour deposition (CVD) systems, both designed and constructed by the author. Initial experiments confirmed that no degradation in the bulk minority carrier lifetime (????bulk) occurred during high-temperature processing, although the stability of the USD-deposited TiO2 films was dependent on the furnace ambient. A major disadvantage of TiO2 AR coatings is that they afford little surface passivation. In this work, a novel method of achieving excellent surface passivation on TiO2-coated silicon wafers is presented. This involved growing a 6 nm-thick SiO2 layer at the TiO2:Si interface by oxidising the wafer after TiO2 film deposition. The increase in surface passivation afforded by the interfacial SiO2 layer results in a decrease in the emitter dark saturation current density (J0e) by nearly two orders of magnitude to 4.7 ??? 7.7 ??~ 10???14 A/cm2. This demonstrates the compatibility of the TiO2/SiO2 stack with high-efficiency solar cells designs. By varying the film deposition and annealing conditions, TiO2 refractive indices in the range of 1.726 ??? 2.633 (at ???? = 600 nm) could be achieved. Subsequently, a double-layer antireflection (DLAR) coating was designed comprised of low and high TiO2 refractive index material. The best experimental weighted average reflectance (Rw) achieved was 6.5% on a planar silicon wafer in air. TiO2 DLAR coatings are ideally suited to multicrystalline silicon (mc-Si) wafers, which do not respond well to chemical texturing. Modelling performed for a glass and ethyl vinyl acetate (EVA) encapsulated buried-contact solar cell indicated that a TiO2 DLAR coating afforded a 7% increase in the short circuit current density, when compared to a standard, commercially-deposited TiO2 single-layer AR coating. Finally, it is demonstrated that chemical reactions with phosphorus prevent TiO2 from acting as a successful phosphorus diffusion barrier or dopant source. The applicability of TiO2 thin films to various silicon solar cell structures is discussed.

Thesis (M.S.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 67-73). Also available on the World Wide Web.

Thesis (Ph. D.)--University of Washington, 2005. / Vita. Includes bibliographical references (leaves 221-230).

A unique process of fabricating a strained layer GexSi1-x on insulator is demonstrated. Such strained heterostructures are useful in the fabrication of high-mobility transistors. This technique incorporates well-established silicon processing technology e.g., ion implantation and thermal oxidation. A dilute GeSi layer is initially formed by implanting Ge+ into a silicon-on-insulator (SOI) substrate. Thermal oxidation segregates the Ge at the growing oxide interface to form a distinct GexSi1-x thin-film with a composition that can be tailored by controlling the oxidation parameters (e.g. temperature and oxidation ambient). In addition, the film thickness can be controlled by implantation fluence, which is important since the film forms pseudomorphically below 2×1016 Ge/cm2. Continued oxidation consumes the underlying Si leaving the strained GeSi film encapsulated by the two oxide layers, i.e. the top thermal oxide and the buried oxide. Removal of the thermal oxide by a dilute HF etch completes the process. Strain relaxation can be achieved by either of two methods. One involves vacancy injection by ion implantation to introduce sufficient open-volume within the film to compensate for the compressive strain. The other depends upon the formation of GeO2. If Ge is oxidized in the absence of Si, it evaporates as GeO(g) resulting in spontaneous relaxation within the strained film. Conditions under which this occurs have been discussed along with elaborated results of oxidation kinetics of Ge-ion implanted silicon. Rutherford backscattering spectrometry (RBS), ion channeling, Raman spectroscopy and scanning electron microscopy (SEM) were used as the characterization techniques.

This thesis examines the excimer-laser-induced melting of ELA-prepared silicon films using in situ transient reflectance and transmission analysis. The results clearly show that these polycrystalline films, which consist of columnar grains in contact with SiO₂, can melt in a largely and remarkably 2-D manner. Based on the presently and previously obtained experimental results, as well as considering the thermal, thermodynamic, and kinetic aspects of the melting-transition-relevant details, we suggest a model that consists of grain-boundary-initiated melting, followed by lateral melting proceeding into the transiently superheated interior of the grains. Additional experiments are performed which demonstrate how this 2-D melting behavior at least stems intrinsically from the presence in the material of melt-prone grain boundaries and superheating-permitting Si/SiO₂ interfaces. Next, the phase and temperature evolutions of the irradiated films are investigated using a numerical simulation program, which incorporates key material, thermodynamic, and kinetic parameters. We find that the center portion of the grains during (partial) melting (1) corresponds to, especially at the SiO₂-passivated surface, the hottest regions of the films during rapid heating, and (2) remains entirely solid throughout the thickness of the film, as the maximum temperature sustained in these unmelted solids remains well below the superheating limit of silicon at the Si/SiO₂ interface. Lastly, we discuss, and substantiate with results obtained from numerical simulations, the role that the manifested dimensionality of melting plays in dictating the efficiency with which the ELA crystallization technique can generate microstructurally uniform polycrystalline materials. The current discovery regarding the 2-D nature of melting should be recognized and appreciated as a critical process-enabling element for ELA, as the scenario permits microstructure evolution of the grains to take place in an effective manner.

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Silicon Oxide/Oxynitride (SiO2/SiON) has been the mainstream material used for gate dielectric for MOS transistors for the past 30 years. The aggressive scaling of the feature size of MOS transistor has limited the ability of SiO2/SiON to work effectively as the gate dielectric to modulate the conduction of current of MOS transistors due to excess leakage current dominated by direct quantum tunneling. Due to this constraint, alternative gate dielectric/high-k is being employed to reduce the leakage current in order to maintain the rate of scaling of MOS transistors. However, the cost involved in the implementation of these new gate dielectric materials are high due to the requirements of a change in the process flow for device fabrication. This work presents the results of a novel processing method implementing the use of rapid thermal processing (RTP) on conventional SiO2/SiON gate dielectric to reduce the gate leakage current by three to five orders of magnitude. Electrical properties of the effect were characterized on fabricated MOS capacitors using semiconductor parameter analyzer and LCR meter. Material characterization was performed using FT-IR to understand the mechanism involved in this novel processing method, named PECE (Phonon-Energy-Coupling-Enhancement). By implementing this novel process, the use of SiO2/SiON as gate dielectric can be scaled further in conventional process flow of device fabrication.