Techn. University, Diss., 2003--Darmstadt.

The design of microprocessors is undergoing radical changes that affect the performance and reliability of hardware and will have a high impact on software development. Future systems will depend on a deep collaboration between software and hardware to cope with the current and predicted system design challenges. Instead of higher frequencies, the number of processor cores per chip is growing. Eventually, processors will be composed of cores that run at different speeds or support specialized features to accelerate critical portions of an application. Performance improvements of software will only result from increasing parallelism and introducing asymmetric processing. At the same time, substantial enhancements in the energy efficiency of hardware are required to make use of the increasing transistor density. Unfortunately, the downscaling of transistor size and power will degrade the reliability of the hardware, which must be compensated by software. In this thesis, we present new algorithms and tools that exploit speculative and asymmetric execution to address the performance and reliability challenges of multicore architectures. Our solutions facilitate both the assimilation of software to the changing hardware properties as well as the adjustment of hardware to the software it executes. We use speculation based on transactional memory to improve the synchronization of multi-threaded applications. We show that shared memory synchronization must not only be scalable to large numbers of cores but also robust such that it can guarantee progress in the presence of hardware faults. Therefore, we streamline transactional memory for a better throughput and add fault tolerance mechanisms with a reduced overhead by speculating optimistically on an error-free execution. If hardware faults are present, they can manifest either in a single event upset or crashes and misbehavior of threads. We address the former by applying transactions to checkpoint and replicate the state such that threads can correct and continue their execution. The latter is tackled by extending the synchronization such that it can tolerate crashes and misbehavior of other threads. We improve the efficiency of transactional memory by enabling a lightweight thread that always wins conflicts and significantly reduces the overheads. Further performance gains are possible by exploiting the asymmetric properties of applications. We introduce an asymmetric instrumentation of transactional code paths to enable applications to adapt to the underlying hardware. With explicit frequency control of individual cores, we show how applications can expose their possibly asymmetric computing demand and dynamically adjust the hardware to make a more efficient usage of the available resources.

Ferroelectrics are promising for nonvolatile memories. However, the diffi culty of fabricating ferroelectric layers and integrating them into complementary metal oxide semiconductor (CMOS) devices has hindered rapid scaling. Hafnium oxide is a standard material available in CMOS processes. Ferroelectricity in Si-doped hafnia was first reported in 2011, and this has revived interest in using ferroelectric memories for various applications. Ferroelectric hafnia with matured atomic layer deposition techniques is compatible with three-dimensional capacitors and can solve the scaling limitations in 1-transistor-1-capacitor (1T-1C) ferroelectric random-access memories (FeRAMs). For ferroelectric field-effect-transistors (FeFETs), the low permittivity and high coercive field Ec of hafnia ferroelectrics are beneficial. The much higher Ec of ferroelectric hafnia, however, makes high endurance a challenge. This article summarizes the current status of ferroelectricity in hafnia and explains how major issues of 1T-1C FeRAMs and FeFETs can be solved using this material system.

Der vorliegende Posterbeitrag beschäftigt sich mit der Entwicklung angepasster Entwicklungsmethoden für nachhaltig aufgebaute Hochvolt-Speicher. Dazu wird zunächst analysiert, welche technischen Kriterien bei der Produktgestaltung vor dem Hintergrund der Wiederverwendbarkeit einzelner Komponenten besondere Berücksichtigung finden müssen. Unter Zuhilfenahme der Recycling-Kaskade aus der VDI 2243 wird die Entscheidungsfindung im Konstruktionsprozess methodisch ergänzt sowie die notwendigen Betrachtungen, die das Vorgehen objektiv bewerten, vorgestellt. Die Notwendigkeit eines zeitlichen und kostenseitigen Montage-Demontage-Abgleichs ist für die Erreichung der Ziele unabdingbar, da im Rahmen des Entwicklungsprozesses keine Suboptima entstehen sollen. Im Anschluss wird an einem Beispiel aus dem direkten Forschungsumfeld der Autoren, ein 48V-Submodul eines HV-Speichers, das Vorgehen und die Rückschlüsse für die Entwicklung und Konstruktion veranschaulicht. Abschließend werden die gewonnenen Erkenntnisse für die Konstruktionssystematik von HV-Speichern verallgemeinert und dienen der Beantwortung folgender Fragen: Welche Größen beeinflussen unmittelbar die Instandsetzung- und damit die Wieder- bzw. Weiterverwendbarkeit? — Welche Aspekte müssen zur Sicherstellung der Nachhaltigkeit (z.B. Langlebigkeit und Zweitnutzung der Module etc.) zwangsweise berücksichtig werden? — Wie kann sichergestellt werden, dass mit nicht formstabilen und thermisch komplexen Einzelteilen (Zellen) eine sichere Demontagefähigkeit gewährleitet ist? — Welche Detektierungsverfahren und –methoden sind notwendig?

We report on a two-layer based ferroelectric tunnel junction with hafnium zirconium oxide (HZO) as the ferroelectric layer and aluminum oxide as the tunneling layer. The experimental results focus on optimizing the thicknesses of the layer stack. The device operation relies on the polarization reversal of the HZO layer, while electron tunneling occurs through the dielectric layer. The ferroelectric response of the HZO shows high remanent polarization values and good endurance with only weak wake-up and fatigue behavior. Adding the additional dielectric tunneling layer, the device becomes operational as a ferroelectric tunnel junction in the nanoampere current range. It shows good on/off ratios and promising retention behavior, paving the way for future applications as a polarization-based resistive memory device.

Hybrid memory systems consisting of DRAM and NVRAM offer a great opportunity for column-oriented data systems to persistently store and to efficiently process columnar data completely in main memory. While vectorization (SIMD) of query operators is state-of-the-art to increase the single-thread performance, it has to be combined with thread-level parallelism (MIMD) to satisfy growing needs for higher performance and scalability. However, it is not well investigated how such a SIMD-MIMD interplay could be leveraged efficiently in hybrid memory systems. On the one hand, we deliver an extensive experimental evaluation of typical workloads on columnar data in this paper. We reveal that the choice of the most performant SIMD version differs greatly for both memory types. Moreover, we show that the throughput of concurrent queries can be boosted (up to 2x) when combining various SIMD flavors in a multi-threaded execution. On the other hand, to enable that optimization, we propose an adaptive SIMD-MIMD cocktail approach incurring only a negligible runtime overhead.

Es werden Probleme der Langzeitarchivierung diskutiert, sowohl aus Anwendersicht als auch Betreibersicht. Konkret wird das Speicherungskonzept von MONARCH vorgestellt, mit dem versucht wird, die aufgeworfenen Probleme der Langzeitarchivierung zu loesen.

In dieser Arbeit wurde das laserinduzierte Fluoreszenzlicht von mikrometergroßen Partikeln untersucht, die in einer elektrodynamischen Vierpolfalle gespeichert waren. Untersuchungsobjekte dabei waren ligandenstabilisierte Cadmiumsulfid-Cluster, Farbstoffpartikel und Diamanten mit N-V-Zentren. Auf die Herstellung und Charakterisierung der CdS-Proben wird genauer eingegangen. Zum Probentransfer in den Speicher wurde die Verwendung eines kommerziellen Tröpfchengenerators eingeführt und diskutiert.

Im Rahmen dieser vorliegenden Arbeit soll untersucht werden, welche Möglichkeiten zur Sicherung einer möglichst hohen Verfügbarkeit (High-Availability), Mechanismen zur Lastverteilung mittels des ZEO-Produkts oder ähnlichem sowie welche Strategien des Cachings sinnvoll an einem ZOPE-Server zum Einsatz kommen können. Die Arbeit untersucht dabei die Einsatzmöglichkeiten von bereits vorhandenen und die eventuelle Notwendigkeit der Eigenimplementierung weiterer Produkte der ZOPE-Entwicklung. Den Rahmen der Arbeit bildet die Serverstruktur des Bildungsmarktplatzes Sachsen.

Real-time aspects are becoming more important in standard desktop PC environments and x86 based processors are being utilized in embedded systems more often. While these processors were not created for use in hard real time systems, they are fast and inexpensive and can be used if it is possible to determine the worst case execution time. Information on CPU caches (L1, L2) and branch prediction architecture is necessary to simulate best and worst cases in execution timing, but is often not detailed enough and sometimes not published at all. This document describes how the underlying hardware can be analysed to obtain this information.