Univ., Diss., 2000--Kassel

Univ., Diss., 2005--Kassel

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.:1 Introduction 2 Fundamentals 2.1 Non-volatile semiconductor memories 2.2 Emerging memory concepts 2.3 Ferroelectric memories 3 Characterisation methods 3.1 Memory characterisation tests 3.2 Ferroelectric memory specific characterisation tests 3.3 Trapping characterisation methods 3.4 Microstructural analyses 4 Sample description 4.1 Metal-insulator-metal capacitors 4.2 Ferroelectric field effect transistors 5 Stabilisation of the ferroelectric properties in Si:HfO2 thin films 5.1 Impact of the silicon doping 5.2 Impact of the post-metallisation anneal 5.3 Impact of the film thickness 5.4 Summary 6 Electrical properties of the ferroelectric Si:HfO2 thin films 6.1 Field cycling effect 6.2 Switching kinetics 6.3 Fatigue behaviour 6.4 Summary 7 Ferroelectric field effect transistors based on Si:HfO2 films 7.1 Effect of the silicon doping 7.2 Program and erase operation 7.3 Retention behaviour 7.4 Endurance properties 7.5 Impact of scaling on the device performance 7.6 Summary 8 Trapping effects in Si:HfO2-based FeFETs 8.1 Trapping kinetics of the bulk Si:HfO2 traps 8.2 Detrapping kinetics of the bulk Si:HfO2 traps 8.3 Impact of trapping on the FeFET performance 8.4 Modified approach for erase operation 8.5 Summary 9 Summary and Outlook

Im Forschungs- und Demonstrationsprogramm Solarthermie 2000, Teilprogramm 3 wurden von 1993 bis 2002 solar unterstützte Nahwärmesysteme konzipiert, errichtet und vermessen. Wesentliche Ziele dieses Programms waren die Demonstration der Durchführbarkeit, der Nachweis der Kostenreduktion bei großen Systemen und die Weiterentwicklung sowie Untersuchung dieser Technik. Das in diesem Bericht dokumentierte Forschungsvorhaben ist ein Projekt in oben genanntem Vorhaben und zeichnet sich durch folgende Parameter aus: - Energiequelle: Kollektorfelder mit einer Absorberfläche von 538,5 m² (Vakuum-Röhrenkollektoren) und BHKW, - saisonaler Speicher: 8000 m³ Kies-Wasser-Speicher, - Verbraucher: Heizung eines Bürogebäudes Das Vorhaben wurde durch die Autoren wissenschaftlich-technisch betreut. Die Erkenntnisse von der Konzeption bis zur funktionstüchtigen Anlage werden im Bericht erläutert. Auf Grund der meßtechnischen Untersuchung liegen detaillierte Ergebnisse zum Systemverhalten, zur Effizienz der Bauteile und des Systems vor.

Im Forschungs- und Demonstrationsprogramm Solarthermie 2000, Teilprogramm 3 wurden von 1993 bis 2002 solar unterstützte Nahwärmesysteme konzipiert, errichtet und vermessen. Wesentliche Ziele dieses Programms waren die Demonstration der Durchführbarkeit, der Nachweis der Kostenreduktion bei großen Systemen und die Weiterentwicklung sowie Untersuchung dieser Technik. Das in diesem Bericht dokumentierte Forschungsvorhaben ist ein Projekt in oben genanntem Vorhaben und zeichnet sich durch folgende Parameter aus: - Energiequelle: Kollektorfelder mit einer Absorberfläche von 538,5 m² (Vakuum-Röhrenkollektoren) und BHKW, - saisonaler Speicher: 8000 m³ Kies-Wasser-Speicher, - Verbraucher: Heizung eines Bürogebäudes Das Vorhaben wurde durch die Autoren wissenschaftlich-technisch betreut. Die Erkenntnisse von der Konzeption bis zur funktionstüchtigen Anlage werden im Bericht erläutert. Auf Grund der meßtechnischen Untersuchung liegen detaillierte Ergebnisse zum Systemverhalten, zur Effizienz der Bauteile und des Systems vor.

With the rise of computationally expensive application domains such as machine learning, genomics, and fluids simulation, the quest for performance and energy-efficient computing has gained unprecedented momentum. The significant increase in computing and memory devices in modern systems has resulted in an unsustainable surge in energy consumption, a substantial portion of which is attributed to the memory system. The scaling of conventional memory technologies and their suitability for the next-generation system is also questionable. This has led to the emergence and rise of nonvolatile memory ( NVM ) technologies. Today, in different development stages, several NVM technologies are competing for their rapid access to the market. Racetrack memory ( RTM ) is one such nonvolatile memory technology that promises SRAM -comparable latency, reduced energy consumption, and unprecedented density compared to other technologies. However, racetrack memory ( RTM ) is sequential in nature, i.e., data in an RTM cell needs to be shifted to an access port before it can be accessed. These shift operations incur performance and energy penalties. An ideal RTM , requiring at most one shift per access, can easily outperform SRAM . However, in the worst-cast shifting scenario, RTM can be an order of magnitude slower than SRAM . This thesis presents an overview of the RTM device physics, its evolution, strengths and challenges, and its application in the memory subsystem. We develop tools that allow the programmability and modeling of RTM -based systems. For shifts minimization, we propose a set of techniques including optimal, near-optimal, and evolutionary algorithms for efficient scalar and instruction placement in RTMs . For array accesses, we explore schedule and layout transformations that eliminate the longer overhead shifts in RTMs . We present an automatic compilation framework that analyzes static control flow programs and transforms the loop traversal order and memory layout to maximize accesses to consecutive RTM locations and minimize shifts. We develop a simulation framework called RTSim that models various RTM parameters and enables accurate architectural level simulation. Finally, to demonstrate the RTM potential in non-Von-Neumann in-memory computing paradigms, we exploit its device attributes to implement logic and arithmetic operations. As a concrete use-case, we implement an entire hyperdimensional computing framework in RTM to accelerate the language recognition problem. Our evaluation shows considerable performance and energy improvements compared to conventional Von-Neumann models and state-of-the-art accelerators.

Exploiting thread-level parallelism has become a part of mainstream programming in recent years. Many approaches to parallelization require threads executing in parallel to also synchronize occassionally (i.e., coordinate concurrent accesses to shared state). Transactional Memory (TM) is a programming abstraction that provides the concept of database transactions in the context of programming languages such as C/C++. This allows programmers to only declare which pieces of a program synchronize without requiring them to actually implement synchronization and tune its performance, which in turn makes TM typically easier to use than other abstractions such as locks. I have investigated and implemented the building blocks that are required for a high-performance, practical, and realistic TM. They host several novel algorithms and optimizations for TM implementations, both for current hardware and future hardware extensions for TM, and are being used in or have influenced commercial TM implementations such as the TM support in GCC.

Es werden Probleme der Langzeitarchivierung diskutiert, sowohl aus Anwendersicht als auch Betreibersicht. Konkret wird das Speicherungskonzept von MONARCH vorgestellt, mit dem versucht wird, die aufgeworfenen Probleme der Langzeitarchivierung zu loesen.

In dieser Arbeit wurde das laserinduzierte Fluoreszenzlicht von mikrometergroßen Partikeln untersucht, die in einer elektrodynamischen Vierpolfalle gespeichert waren. Untersuchungsobjekte dabei waren ligandenstabilisierte Cadmiumsulfid-Cluster, Farbstoffpartikel und Diamanten mit N-V-Zentren. Auf die Herstellung und Charakterisierung der CdS-Proben wird genauer eingegangen. Zum Probentransfer in den Speicher wurde die Verwendung eines kommerziellen Tröpfchengenerators eingeführt und diskutiert.