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Visualization of domain structure evolution under an electrical bias has been carried out in ferroelectric La:HfO2 capacitors by a combination of Piezoresponse Force Microscopy (PFM) and pulse switching techniques to study the nanoscopic mechanism of polarization reversal and the wake-up process. It has been directly shown that the main mechanism behind the transformation of the polarization hysteretic behavior and an increase in the remanent polarization value upon the alternating current cycling is electrically induced domain de-pinning. PFM imaging and local spectroscopy revealed asymmetric switching in the La:HfO2 capacitors due to a significant imprint likely caused by the different boundary conditions at the top and bottom interfaces. Domain switching kinetics can be well-described by the nucleation limited switching model characterized by a broad distribution of the local switching times. It has been found that the domain velocity varies significantly throughout the switching process indicating strong interaction with structural defects.

Ferroelectrics are promising for nonvolatile memories. However, the difficulty of fabricating ferroelectric layers and integrating them into complementary metal oxide semiconductor (CMOS) devices has hindered rapid scaling. Hafnium oxide is a standard material available in CMOS processes. Ferroelectricity in Si-doped hafnia was first reported in 2011, and this has revived interest in using ferroelectric memories for various applications. Ferroelectric hafnia with matured atomic layer deposition techniques is compatible with three-dimensional capacitors and can solve the scaling limitations in 1-transistor-1-capacitor (1T-1C) ferroelectric random-access memories (FeRAMs). For ferroelectric field-effect-transistors (FeFETs), the low permittivity and high coercive field Ec of hafnia ferroelectrics are beneficial. The much higher Ec of ferroelectric hafnia, however, makes high endurance a challenge. This article summarizes the current status of ferroelectricity in hafnia and explains how major issues of 1T-1C FeRAMs and FeFETs can be solved using this material system.

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.:1 Introduction 2 Fundamentals 2.1 Non-volatile semiconductor memories 2.2 Emerging memory concepts 2.3 Ferroelectric memories 3 Characterisation methods 3.1 Memory characterisation tests 3.2 Ferroelectric memory specific characterisation tests 3.3 Trapping characterisation methods 3.4 Microstructural analyses 4 Sample description 4.1 Metal-insulator-metal capacitors 4.2 Ferroelectric field effect transistors 5 Stabilisation of the ferroelectric properties in Si:HfO2 thin films 5.1 Impact of the silicon doping 5.2 Impact of the post-metallisation anneal 5.3 Impact of the film thickness 5.4 Summary 6 Electrical properties of the ferroelectric Si:HfO2 thin films 6.1 Field cycling effect 6.2 Switching kinetics 6.3 Fatigue behaviour 6.4 Summary 7 Ferroelectric field effect transistors based on Si:HfO2 films 7.1 Effect of the silicon doping 7.2 Program and erase operation 7.3 Retention behaviour 7.4 Endurance properties 7.5 Impact of scaling on the device performance 7.6 Summary 8 Trapping effects in Si:HfO2-based FeFETs 8.1 Trapping kinetics of the bulk Si:HfO2 traps 8.2 Detrapping kinetics of the bulk Si:HfO2 traps 8.3 Impact of trapping on the FeFET performance 8.4 Modified approach for erase operation 8.5 Summary 9 Summary and Outlook