Informationen des Universitätsrechenzentrums

Informationen des Universitätsrechenzentrums

Database systems have long been optimized to hide the higher latency of storage media, yielding complex persistence mechanisms. With the advent of large DRAM capacities, it became possible to keep a full copy of the data in DRAM. Systems that leverage this possibility, such as main-memory databases, keep two copies of the data in two different formats: one in main memory and the other one in storage. The two copies are kept synchronized using snapshotting and logging. This main-memory-centric architecture yields nearly two orders of magnitude faster analytical processing than traditional, disk-centric ones. The rise of Big Data emphasized the importance of such systems with an ever-increasing need for more main memory. However, DRAM is hitting its scalability limits: It is intrinsically hard to further increase its density. Storage-Class Memory (SCM) is a group of novel memory technologies that promise to alleviate DRAM’s scalability limits. They combine the non-volatility, density, and economic characteristics of storage media with the byte-addressability and a latency close to that of DRAM. Therefore, SCM can serve as persistent main memory, thereby bridging the gap between main memory and storage. In this dissertation, we explore the impact of SCM as persistent main memory on database systems. Assuming a hybrid SCM-DRAM hardware architecture, we propose a novel software architecture for database systems that places primary data in SCM and directly operates on it, eliminating the need for explicit IO. This architecture yields many benefits: First, it obviates the need to reload data from storage to main memory during recovery, as data is discovered and accessed directly in SCM. Second, it allows replacing the traditional logging infrastructure by fine-grained, cheap micro-logging at data-structure level. Third, secondary data can be stored in DRAM and reconstructed during recovery. Fourth, system runtime information can be stored in SCM to improve recovery time. Finally, the system may retain and continue in-flight transactions in case of system failures. However, SCM is no panacea as it raises unprecedented programming challenges. Given its byte-addressability and low latency, processors can access, read, modify, and persist data in SCM using load/store instructions at a CPU cache line granularity. The path from CPU registers to SCM is long and mostly volatile, including store buffers and CPU caches, leaving the programmer with little control over when data is persisted. Therefore, there is a need to enforce the order and durability of SCM writes using persistence primitives, such as cache line flushing instructions. This in turn creates new failure scenarios, such as missing or misplaced persistence primitives. We devise several building blocks to overcome these challenges. First, we identify the programming challenges of SCM and present a sound programming model that solves them. Then, we tackle memory management, as the first required building block to build a database system, by designing a highly scalable SCM allocator, named PAllocator, that fulfills the versatile needs of database systems. Thereafter, we propose the FPTree, a highly scalable hybrid SCM-DRAM persistent B+-Tree that bridges the gap between the performance of transient and persistent B+-Trees. Using these building blocks, we realize our envisioned database architecture in SOFORT, a hybrid SCM-DRAM columnar transactional engine. We propose an SCM-optimized MVCC scheme that eliminates write-ahead logging from the critical path of transactions. Since SCM -resident data is near-instantly available upon recovery, the new recovery bottleneck is rebuilding DRAM-based data. To alleviate this bottleneck, we propose a novel recovery technique that achieves nearly instant responsiveness of the database by accepting queries right after recovering SCM -based data, while rebuilding DRAM -based data in the background. Additionally, SCM brings new failure scenarios that existing testing tools cannot detect. Hence, we propose an online testing framework that is able to automatically simulate power failures and detect missing or misplaced persistence primitives. Finally, our proposed building blocks can serve to build more complex systems, paving the way for future database systems on SCM.

Logic-in-memory circuits promise to overcome the von-Neumann bottleneck, which constitutes one of the limiting factors to data throughput and power consumption of electronic devices. In the following we present four-input logic gates based on only two ferroelectric FETs (FeFETs) with hafnium oxide as the ferroelectric material. By utilizing two complementary inputs, a XOR and a XNOR gate are created. The use of only two FeFETs results in a compact and nonvolatile design. This realization, moreover, directly couples the memory and logic function of the FeFET. The feasibility of the proposed structures is revealed by electrical measurements of HKMG FeFET memory arrays manufactured in 28nm technology.

During the last decade ferroelectrics based on doped hafnium oxide emerged as promising candidates for realization of ultra-low-power non-volatile memories. Two spontaneous polarization states occurring in the material that can be altered by applying electrical fields rather than forcing a current through and the materials compatibility to CMOS processing are the main benefits setting the concept apart from other emerging memories. 1T1C ferroelectric random access memories (FeRAM) as well as 1T FeFET concepts are under investigation. In this article the application of hafnium based ferroelectric memories in different flavours and their ranking in the memory landscape are discussed.

The influence of depolarization and its role in causing data retention failure in ferroelectric memories is investigated. Ferroelectric Hf₀.₅Zr₀.₅O₂ thin films 8 nm thick incorporated into a metal-ferroelectric-metal capacitor are fabricated and characterized with varying thicknesses of an Al₂O₃ interfacial layer. The magnitude of the depolarization field is adjusted by controlling the thickness of the Al₂O₃ layer. The initial polarization and the change in polarization with electric field cycling is strongly impacted by the insertion of Al₂O₃ within the device stack. Transient polarization loss is shown to get worse with larger depolarization fields and data retention is evaluated up to 85 °C.

Parallel, adaptive Level-of-Detail in VR simulations. Parameters for efficient reuse of already calculated reductions are investigated. Choosen reduction algorithms are evaluated. Parameters for communication within the distributed application are determined. An implementation is introduced. / Paralleles, adaptives Level-of-Detail komplexer Objekten in VR-Simulationen. Die Parameter für eine effiziente Wiederverwendung bereits berechneter Reduktionen werden untersucht. Ausgewählte Reduktionsalgorithmen werden evaluiert. Die Parameter für die Kommunikation in der verteilten Applikation werden ermittelt. Eine Implementation wird vorgestellt.

Die konventionelle Kälteerzeugung mit Kompressionskältemaschinen ist mit vielen Nachteilen verbunden: hohe elektrische Lastspitzen, Energieverbräuche, Umweltbelastungen, signifikante Kosten sowie ein umfangreicher Einsatz von ozonabbauenden Kältemitteln in den letzten Jahren. Eine wesentliche Verbesserung kann durch die Kraft-Wärme-Kälte-Kopplung erreicht werden. Durch die thermisch angetriebenen Kältemaschinen ist eine rationelle Nutzung der im Kühllastfall ausreichend vorhandenen Wärme möglich. Um die Kälteerzeugung weiter energetisch, wirtschaftlich und ökologisch zu verbessern, stellt der Einsatz von Kältespeichern eine aussichtsreiche Alternative dar. In diesem Projekt wird deshalb der Kältespeicher-Einsatz speziell für die Randbedingungen in Deutschland untersucht.

Informationen des Universitätsrechenzentrums:Neuer Dienst: WXPSelfAdmin - Management von WXP-Rechnern mit lokalen Admin-Rechten Aufbau eines Storage Area Networks (SAN) Software in den Computerpools Was tun gegen Spam? Software-News: Neue Software-Handbücher, CATIA, Docolog Kurzinformationen: X-WiN-Anschluss mit 2Gbit/s, Umstellung der OpenSSH-Version

The design of microprocessors is undergoing radical changes that affect the performance and reliability of hardware and will have a high impact on software development. Future systems will depend on a deep collaboration between software and hardware to cope with the current and predicted system design challenges. Instead of higher frequencies, the number of processor cores per chip is growing. Eventually, processors will be composed of cores that run at different speeds or support specialized features to accelerate critical portions of an application. Performance improvements of software will only result from increasing parallelism and introducing asymmetric processing. At the same time, substantial enhancements in the energy efficiency of hardware are required to make use of the increasing transistor density. Unfortunately, the downscaling of transistor size and power will degrade the reliability of the hardware, which must be compensated by software. In this thesis, we present new algorithms and tools that exploit speculative and asymmetric execution to address the performance and reliability challenges of multicore architectures. Our solutions facilitate both the assimilation of software to the changing hardware properties as well as the adjustment of hardware to the software it executes. We use speculation based on transactional memory to improve the synchronization of multi-threaded applications. We show that shared memory synchronization must not only be scalable to large numbers of cores but also robust such that it can guarantee progress in the presence of hardware faults. Therefore, we streamline transactional memory for a better throughput and add fault tolerance mechanisms with a reduced overhead by speculating optimistically on an error-free execution. If hardware faults are present, they can manifest either in a single event upset or crashes and misbehavior of threads. We address the former by applying transactions to checkpoint and replicate the state such that threads can correct and continue their execution. The latter is tackled by extending the synchronization such that it can tolerate crashes and misbehavior of other threads. We improve the efficiency of transactional memory by enabling a lightweight thread that always wins conflicts and significantly reduces the overheads. Further performance gains are possible by exploiting the asymmetric properties of applications. We introduce an asymmetric instrumentation of transactional code paths to enable applications to adapt to the underlying hardware. With explicit frequency control of individual cores, we show how applications can expose their possibly asymmetric computing demand and dynamically adjust the hardware to make a more efficient usage of the available resources.