While there is a wide variety of both open source and proprietary source code static analyzers available in the market, each of them usually performs better in a small set of problems, making it hard to choose one single tool to rely on when examining a program. Combining the analysis of different tools may reduce the number of false negatives, but yields a corresponding increase in the number of false positives (which is already high for many tools). An interesting solution, then, is to filter these results to identify the issues least likely to be false positives. This work presents kiskadee, a system to support the usage of static analysis during software development by providing carefully ranked static analysis reports. First, it runs multiple static analyzers on the source code. Then, using a classification model, the potential bugs detected by the static analyzers are ranked based on their importance, with critical flaws ranked first, and potential false positives ranked last. To train kiskadee\'s classification model, we post-analyze the reports generated by three tools on synthetic test cases provided by the US National Institute of Standards and Technology. To make our technique as general as possible, we limit our data to the reports themselves, excluding other information such as change histories or code metrics. The features extracted from these reports are used to train a set of decision trees using AdaBoost to create a stronger classifier, achieving 0.8 classification accuracy (the combined false positive rate from the used tools was 0.61). Finally, we use this classifier to rank static analyzer alarms based on the probability of a given alarm being an actual bug. Our experimental results show that, on average, when inspecting warnings ranked by kiskadee, one hits 5.2 times less false positives before each bug than when using a randomly sorted warning list. / Embora exista grande variedade de analisadores estáticos de código-fonte disponíveis no mercado, tanto com licenças proprietárias, quanto com licenças livres, cada uma dessas ferramentas mostra melhor desempenho em um pequeno conjunto de problemas distinto, dificultando a escolha de uma única ferramenta de análise estática para analisar um programa. A combinação das análises de diferentes ferramentas pode reduzir o número de falsos negativos, mas gera um aumento no número de falsos positivos (que já é alto para muitas dessas ferramentas). Uma solução interessante é filtrar esses resultados para identificar os problemas com menores probabilidades de serem falsos positivos. Este trabalho apresenta kiskadee, um sistema para promover o uso da análise estática de código fonte durante o ciclo de desenvolvimento de software provendo relatórios de análise estática ranqueados. Primeiramente, kiskadee roda diversos analisadores estáticos no código-fonte. Em seguida, utilizando um modelo de classificação, os potenciais bugs detectados pelos analisadores estáticos são ranqueados conforme sua importância, onde defeitos críticos são colocados no topo de uma lista, e potenciais falsos positivos, ao fim da mesma lista. Para treinar o modelo de classificação do kiskadee, realizamos uma pós-análise nos relatórios gerados por três analisadores estáticos ao analisarem casos de teste sintéticos disponibilizados pelo National Institute of Standards and Technology (NIST) dos Estados Unidos. Para tornar a técnica apresentada o mais genérica possível, limitamos nossos dados às informações contidas nos relatórios de análise estática das três ferramentas, não utilizando outras informações, como históricos de mudança ou métricas extraídas do código-fonte dos programas inspecionados. As características extraídas desses relatórios foram utilizadas para treinar um conjunto de árvores de decisão utilizando o algoritmo AdaBoost para gerar um classificador mais forte, atingindo uma acurácia de classificação de 0,8 (a taxa de falsos positivos das ferramentas utilizadas foi de 0,61, quando combinadas). Finalmente, utilizamos esse classificador para ranquear os alarmes dos analisadores estáticos nos baseando na probabilidade de um dado alarme ser de fato um bug no código-fonte. Resultados experimentais mostram que, em média, quando inspecionando alarmes ranqueados pelo kiskadee, encontram-se 5,2 vezes menos falsos positivos antes de se encontrar cada bug quando a mesma inspeção é realizada para uma lista ordenada de forma aleatória.

Este trabalho trata da retificação trifásica com elevado fator de potência. São mostradas algumas soluções encontradas na literatura. Dentre elas, optou-se pela utilização de um conversor trifásico autocomutado do tipo fonte de tensão (VSC), operando em modulação em largura de pulso (PWM). Apresenta-se a modelagem do conversor, que é utilizado para o projeto dos controladores responsáveis pelo rastreamento das correntes da rede CA e pela regulação da tensão CC. O projeto do controlador das correntes CA, baseado na estratégia de dead-beat, é mostrado de forma simples e intuitiva e é discutida a estabilidade deste controlador. O projeto do controlador PI utilizado para a regulação da tensão CC é baseado no modelo linearizado do conversor. É utilizado um algoritmo simples e eficiente para o bloco PLL, baseado na estratégia “dead-beat". O comportamento do sistema completo é verificado teoricamente, por simulações numéricas e resultados experimentais, confirmando o excelente desempenho das estratégias de controle e do método de projeto propostos. São discutidos ainda os efeitos da variação nos parâmetros no desempenho e na estabilidade do sistema. / This study investigates three-phase rectifiers with high power factor. Some existing solutions in the literature are presented. One of them, the three-phase voltage source converter (VSC) rectifier with pulse width modulation (PWM) is chosen to be used. Converter modeling is presented and used to design a mains current tracking controller and a DC voltage regulator. AC current controlling based on the deadbeat strategy is presented in a simple and intuitive way, and the stability of this controller is discussed. The DC side PI controller is designed based on the linearized model of the converter. A simple and efficient PLL block algorithm, based on the deadbeat strategy is presented. The behavior of the complete system is verified theoretically, by numerical simulation and experimental results, confirming the excellent performance of the proposed control strategy and method of design. The effects of parameter mismatch on system performance and stability are also discussed.

Asynchronous message passing systems are fast becoming a common means for communication between devices. Two problems existing in message passing programs are difficult to solve. The first problem, intended or otherwise, is message-race where a receive may match with more than one send in the runtime system. This non-determinism often leads to intermittent and unexpected behavior depending on the resolution of the race. Another problem is deadlock, which is a situation in that each member process of the group is waiting for some member process to communicate with it, but no member is attempting to communicate with it. Detecting if message-race and/or deadlocks exist in a message passing program are both NP-complete. The difficulty of solving the two problems also comes from three factors that complicate the semantics: asynchronous communication, synchronous barrier, and buffering settings including infinite buffering (the system can buffer messages) and zero buffering (the system has no internal buffering). To solve the above problems with complicating factors, this research provides a novel predictive analysis that initializes a concrete execution and then predicts the behavior of other executions that arise from the initial execution. This research starts with Satisfiability Modulo Theories (SMT) based model checking that provides precise analysis for the program behavior. Unfortunately, a precise analysis using SMT does not scale to large programs. As such, the SMT based model checking is combined with heuristic search for witnessing program properties. The heuristic search is efficient in identifying how sends may match with receives in the runtime as it only looks for the match relations for sends and receives in a small searching space initially; the space is increased only if the program property is not witnessed, until all possible match relations for sends and receives reflected in message non-determinism are found. This research also gives a static analysis approach that is scalable as it does not need to analyze the full set of program behaviors; rather, the static analysis only uses polynomial-time algorithms to identify all potential deadlocks in a send-receive templates given a set of pre-defined deadlock patterns. Given the predictive analysis consisting of SMT based model checking with heuristic search and static analysis, this research is able to solve the two problems above. The work in this dissertation also demonstrates that the predictive analysis is more efficient than the existing tools for verifying message passing programs.

As vulnerabilities become more common the security of applications are coming under increased scrutiny. In regards to Internet security, recent work discovers that many vulnerabilities are caused by TLS library misuse. This misuse is attributed to large and confusing APIs and developer misunderstanding of security generally. Due to these problems there is a desire for simplified TLS libraries and security handling. However, as of yet there is no analysis of how the existing APIs are used, beyond how incorrect usage motivates the need to replace them. We provide an analysis of contemporary usage of OpenSSL across 410 popular secure applications. These insights will inform the security community as it addresses TLS library redesign.

This work develops and examines design strategies for reducing the stiffness of 3D-printed compliant mechanisms. The three aspects of a flexure that determine its stiffness are well known: material, boundary conditions, and geometry. In a highly constrained design space however, flexure stiffness may remain unacceptably high even while arriving at the limits of design constraints. In this work, changes to geometry and boundary conditions are examined that lead to drastically reduced stiffness behavior without changing flexure thickness, width, or length. Changes to geometry can result in very complex mechanisms. However, 3D printing enables almost arbitrarily complex geometries. This dissertation presents three design strategies for stiffness reduction: static balancing, lattice flexures, and compound joints. Static balancing refers to changes in the boundary conditions that result in a near-zero net change in potential energy storage over the useful deflection of a flexure. In this work, I present a method for static balancing that utilizes non-dimensional parameters to quickly synthesize a joint design with stiffness reduced by nearly 90%. This method is not only simple and straightforward, it is applicable to a wide range of flexure topologies. The only requirements on the joint to be balanced are that it must be approximated as a pin joint and torsion spring, and it must have a well-understood stiffness when subjected to a compressive load. Lattice flexures result from modifications to geometry that reduce cross-sectional area without changing width or thickness. However, the reduction in stiffness is greater than the reduction in cross sectional area. This can occur because the bending load is now carried by beams partially in torsion. Two lattice geometries are proposed and analyzed in detail using analytic and numeric techniques. It is shown that the off-axis stiffness behavior of lattice flexures can be better than that of conventional blade flexures while bending stiffness is reduced >60%. Compound joints are those that consist of arrays of flexures arranged co-axially. This arrangement provides increased range of motion, generally decreased stiffness, and improved stability. Additionally, a method is herein presented to reduce the parasitic center shift of a compound joint to nearly zero at a specified deflection. The penultimate chapter demonstrates how all three strategies can be used together, and includes new results to facilitate their combination.

The contribution of the midfoot in landing mechanics is understudied. Therefore, the main purpose of this study was to quantify midtarsal joint kinematics and kinetics during a barefoot single-leg landing task. A secondary aim of this study was to explore the relationship between static foot posture and dynamic midfoot function. In a cross-sectional study design, 48 females (age = 20.4 ± 1.8 yr, height = 1.6 ± 0.06 m, weight = 57.3 ± 5.5 kg, BMI = 21.6 ± 1.7 kg·m-1) performed drop landings from a height of 0.4 m onto split force platforms. Subjects hung from wooden rings and landed on their dominant leg. Midtarsal joint kinematic and kinetic data were recorded using a motion capture software system in conjunction with a custom multisegment foot model marker set. Arch height index (AHI) for both seated and standing conditions was measured using the Arch Height Index Measurement System (AHIMS). Kinematic data revealed an average sagittal plane midtarsal range of motion (ROM) of 27 degrees through the landing phase. Kinetic data showed that between 7% and 22% of the total power absorption during the landing was performed by the midtarsal joint. Standing AHI was correlated negatively with sagittal plane midtarsal ROM (p = 0.0264) and positively with midtarsal work (p = 0.0212). Standing midfoot angle (MA) was correlated positively with sagittal plane midtarsal ROM (p = 0.0005) and negatively with midtarsal work (p = 0.0250). The midfoot contributes substantially to landing mechanics during a barefoot single-leg landing task. Static foot posture may be a valuable measurement in predicting midfoot kinematics and kinetics.

Abstract available in the Medicine and Sciences in Sports and Exercise.

No description available.

No description available.

Abstract available in the Annual coaches and Sport Science College.