Driven by the need for faster devices and higher transistor densities, technology trends have pushed transistor dimensions into the deep sub-micron regime. This continued scaling, however, has led to many challenges facing digital integrated circuits today. One important challenge is the increased variations in the underlying process and environmental parameters, and the significant impact of this variability on circuit timing and leakage power, making it increasingly difficult to design circuits that achieve a required specification. Given these challenges, there is a need for computer-aided design (CAD) techniques that can predict and analyze circuit performance (timing and leakage) accurately and efficiently in the presence of variability. This thesis presents new techniques for variation-aware timing and leakage analysis that address different aspects of the problem. First, on the timing front, a pre-placement statistical static timing analysis technique is presented. This technique can be applied at an early stage of design, when within-die correlations are still unknown. Next, a general parameterized static timing analysis framework is proposed, which supports a general class of nonlinear delay models and handles both random (process) parameters with arbitrary distributions and non-random (environmental) parameters. Following this, a parameterized static timing analysis technique is presented, which can capture circuit delay exactly at any point in the parameter space. This is enabled by identifying all potentially critical paths in the circuit through novel and efficient pruning algorithms that improve on the state of art both in theoretical complexity and runtime. Also on the timing front, a novel distance-based metric for robustness is proposed. This metric can be used to quantify the susceptibility of parameterized timing quantities to failure, thus enabling designers to fix the nodes with smallest robustness values in order to improve the overall design robustness. Finally, on the leakage front, a statistical technique for early-mode and late-mode leakage estimation is presented. The novelty lies in the random gate concept, which allows for efficient and accurate full-chip leakage estimation. In its simplest form, the leakage estimation reduces to finding the area under a scaled version of the within-die channel length auto-correlation function, which can be done in constant time.

This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in DTA(Dynamic Timing Analysis) and delay look-up table in STA(Static Timing Analysis). Given some equally spaced output values, the traditional Prony's method can be used to extract poles and residues of a linear system, i.e. to characterize a waveform using an exponential function. In this thesis, not only values but also equally spaced derivatives are tested. Still using same idea of the traditional Prony's method, poles and residues can also be extracted with those values and derivatives. The resultant poles and residues will be used to predict the output waveform in DTA analysis. The benefits brought by the using of derivatives include less simulation steps and less CPU time consuming than the regular constant step simulation. As a matter of fact, the Prony's method can precisely approximate a complicated waveform. Such property can be applied for STA analysis. The Prony's approximation can be used to precisely record an output waveform, which is used as an entry of the look-up table of STA. Since the accuracy of STA analysis relies on the accuracy of the input and output waveform in the look-up table, the accuracy of the Prony's approach is promising.

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Strong electron correlations in electronic structure theory are purely quantum effects arising as a result of degeneracies in molecules and materials, and exhibit significantly different yet interesting characters than do weak correlations. Although weak correlations have recently been able to be described very efficiently and accurately within single particle pictures, less known are good prescriptions for treating strong correlations efficiently. Brute-force calculations of strong correlations in wave function theories tend to be very computationally-intensive, and are usually limited to small molecules for applications. Breaking symmetry in a mean-field approximation is an efficient alternative to acquire strong correlations with, in many cases, qualitatively accurate results. The symmetry broken in quantum chemistry has been traditionally of spin, in so-called unrestricted methods, which typically break spatial symmetry as a consequence, and vice versa, in most situations. In this work, we present a novel approach to accurately describing strong correlations with a mean-field cost by means of Hartree- Fock-Bogoliubov (HFB) theory. We are inspired by the number-symmetry-breaking in HFB, which, with an attractive particle interaction, accounts for strong correlations, while maintaining spin and spatial symmetry. We show that this attractive interaction must be restricted to the chemically-relevant orbitals in an active space to obtain physically meaningful results. With such constraints, our constrained pairing mean-field theory (CPMFT) can accurately describe potential energy curves of various strongly-correlated molecular systems, by cleanly separating strong and weak correlations. To achieve the correct dissociation limits in hetero-atomic molecules, we have modified our CPMFT functional by adding asymptotic constraints. We also include weak correlations by combining CPMFT with density functional theory for chemically accurate results, and reveal the connection between CPMFT and traditional unrestricted methods. The similarity between CPMFT and unrestricted methods leads us to the idea of constrained active space unrestricted mean-field approaches. Motivated by CPMFT, we partially retrieve spin-symmetry that has been fully broken in unrestricted methods. We allow symmetry breaking only in an active space. This constrained unrestricted Hartree-Fock (CUHF) is an interpolation between two extrema: the fully broken-symmetry solution and the symmetry preserved solution. This thesis defines the theory behind and reports the results of CUHF. We first show that, if an active space is chosen to include only open-shell electrons, CUHF reduces to restricted open-shell Hartree-Fock (ROHF), and such CUHF proves in many ways significantly

All mechanical systems with moving parts are affected by friction, including industrial robots. Being able to design an accurate friction model would further increase the performance of todays robots. Friction is a complex dynamic phenomena that is constantly changing depending on the state and environment of the robot. It is therefore beneficial to update the parameters of the friction model online. An estimate of the friction will be made using the feedback control signal with the help of a feedforward control scheme in a two axis simulation setup. The friction estimate is then used for an offline identification of three friction model parameters in a static Lugre friction model. Improvements on the identification will be done by introducing some shut-off rules that will improve the estimate. The normalized least mean square method (NLMS) will then be used to update the parameters online. A simulation of friction compensation with a fixed friction model, and with an adaptive friction model will be studied. The method will also be simulated using experimental data taken from a real industrial robot.

The resistor ladder (R/2R) digital-to-analogue converter (DAC) architecture is often used in high performance audio solutions due to its low-noise performance. Even high-end R/2R DACs suffer from static nonlinearity distortions. It was suspected that compensating for these nonlinearities would be possible. It was also suspected that this could improve audio quality in audio systems using R/2R DACs for digital-to-analogue (A/D) conversion. Through the use of models of the resistor ladder architecture a way of characterizing and measuring the faults in the R/2R DAC was created. A compensation algorithm was developed in order to compensate for the nonlinearities. The performance of the algorithm was simulated and an implementation of it was evaluated using an audio evaluation instrument. The results presented show that it is possible to increase linearity in R/2R DACs by compensating for static nonlinearity distortions. The increase in linearity can be quite significant and audible for the trained ear.

This master's thesis deals with timing effects in complex on chip systems. It is written in cooperation with the research and development centre of Infineon Technologies. One primary goal of all integrated circuit designers is to make the chips as small as possible. In deep sub micron designs timing effects like crosstalk have severe impact on the functionality of the chip. Therefore, accurate timing analyses must be made before the chip is ready for manufacturing. Otherwise the production yield can be reduced drastically. A case study on timing analysis with the 0.13 µm technology is made on the bus system of the device S-GOLD. The computer-based program PrimeTime is used to carry out the timing analysis. During the evolution of 0.13 µm technology three design packages have been developed to characterize the timing. Two releases of SGOLD have been designed based on the first and the second design package. The different design packages were compared, with and without pin capacitance variations, on chip variations and crosstalk. Furthermore the two releases are compared. The result from the analysis tool may not correlate well with what you see on the manufactured chips. In order to investigate the correlation, some tests were finally performed on an evaluation board. The results from the timing analysis are as expected. The second netlist version is better optimized than the first one. Design package three is most pessimistic among the three design packages. Design package one is most optimistic and does not match the real performance. Both design package two and three fit to the real performance well. Among the three design packages, design package three fits the real performance best.

There has recently been a resurgence in interest in techniques for effective programming of multi-core computers. Most programmers find general-purpose concurrent programming to be extremely difficult. This difficulty severely limits the number of applications that currently benefit from multi-core computers. There already exist many concurrent solutions for the class of regular applications, which include various algorithms for linear algebra. For the class of irregular applications, which operate on dynamic and pointer- and graph-based structures, efficient concurrent solutions have so far remained elusive. Dataflow analysis applications, which are often found in compilers and program analysis tools, have received particularly little attention with regard to execution on multi-core machines. Operating on the theory that the Actor model, which structures computations as systems of asynchronously-communicating entities, is a more appropriate method for representing irregular algorithms than the shared-memory model, this work presents a concurrent Actor-based formulation of the IFDS, or Interprocedural Finite Distributive Subset, dataflow analysis algorithm. The implementation of this algorithm is done using the Scala language and its Actors library. This algorithm achieves significant speedup on multi-core machines without using any optimistic execution. This work contributes to Actor research by showing how the Actor model can be practically applied to a dataflow analysis problem. This work contributes to static analysis research by showing how a dataflow analysis algorithm can effectively make use of multi-core machines, allowing the possibility of faster and more precise analyses.

Membrane chromatography was investigated as an alternative method to packed-bed chromatography for protein recovery. The purification of lysozyme from egg white with Natrix adseptTM weak cation-exchange membranes was investigated under two different binding configurations: (1) a non-flow, static set-up with variable pH and sodium chloride (NaCl) concentrations during the binding and elution steps, and (2) a dynamic, cross-flow set-up with recycle at pH 7.5 and no NaCl addition during binding. The weak cation-exchange membrane consisted of a carboxylic acid-based, environmentally-responsive hydrogel layer bonded to a polymer matrix. Lysozyme was chosen to illustrate protein-membrane binding interactions due to its well-characterized nature and positive surface charge over a large pH range. For the static binding set-up, two sources of lysozyme were studied: pure lysozyme and egg whites treated with 60 % (v/v) ethanol (ESEW). Elution of bound protein was performed with 1 M NaCl under two pH strategies: binding and elution at a constant pH, and binding at pH 4.5 and variable elution pH. The highest maximum total protein binding capacity for pure lysozyme and ESEW was observed at pH 4.5 with no NaCl addition; however, poor total protein and lysozyme activity recovery were achieved during separation. As well, other egg white proteins, such as ovomucoid, were observed to bind to the membrane surface at pH 4.5, despite possessing similar charge polarity to the anionic membrane surface, indicating a non-electrostatic binding mechanism during operation below the membrane’s pKa (4.7). Based on the conditions tested, the highest total protein and lysozyme activity recovery was demonstrated for the separation of lysozyme from ESEW at pH 7.5 binding and elution and no NaCl addition. In the dynamic binding study, very high pure lysozyme dynamic binding capacity was achieved at 10 % breakthrough (167.3 mg/ml membrane for a 0.35 mg/ml lysozyme solution). The lysozyme dynamic binding capacity was 2.2 times greater than the static binding capacity under similar conditions, significantly higher than published results for other cation-exchange membranes. The separation of lysozyme from four lysozyme sources was tested: pure lysozyme, ESEW, and aqueous egg whites with (ASEW) and without (AEW) 100 mM NaCl. The highest lysozyme activity recovery during separation and lysozyme purity was achieved from the ESEW feed. Lysozyme separation from aqueous egg whites was not as effective, likely due to a high concentration of negatively-charged protein impurities fouling the surface of the membrane. Competitive binding to the membrane limited lysozyme binding and reduced the purity of the recovery elution stream. The application of feed-side pressure during the separation of ESEW produced a high purity, high recovery lysozyme elution stream with a significant reduction in processing time; however, protein aggregates were observed to form on the membrane surface, limiting the applicability of high-pressure operation and reducing protein functionality in the elution stream. The weak cation-exchange membrane system was shown to successfully separate out a target protein from a low concentration protein mixture through electrostatic interactions, and may be further applied to other protein systems.

Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging and testing mechanisms, such as: single-step debugging, breakpoints setting and detection, monitoring, and modification of internal resources. However, the shortcoming of the conventional embedded in circuit emulator (EICE) is that the operation of the processor has to be suspended during debugging, which is categorized as static debugging (Static Debug) and is infeasible for real-time debugging. Therefore, this paper proposes a design alternative to support the real-time system debugging without suspending the microprocessor via the debug hardware Coprocessor14 (the Debug Coprocessor). In this paper, the embedded in circuit emulator is combined with Coprocessor 14 to provide both the static debugging and Run-time system debugging. After incorporating CP14 with the debugging mechanism, the control of the debug hardware is no longer limited to use the IEEE 1149.1 test port during debugging. On the other hand, the set of debugging constraints and the observation of the internal state of the microprocessor can be achieved by inserting the Coprocessor instruction at the program level.