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Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die variations have become dominant and it is imperative to model them to obtain accurate timing analysis results. In addition, intra-die process variations are spatially correlated due to pattern dependencies in the manufacturing process. Any statistical static timing analysis (SSTA) tool is incomplete without a model for signal crosstalk, as critical path delays can increase or decrease depending on the switching of capacitively coupled nets. The coupled signal timing in turn depends on the process variations. This work describes an SSTA tool that models signal crosstalk and spatial correlation in intra-die process variations, along with gradients and inter-die variations.

This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in DTA(Dynamic Timing Analysis) and delay look-up table in STA(Static Timing Analysis). Given some equally spaced output values, the traditional Prony's method can be used to extract poles and residues of a linear system, i.e. to characterize a waveform using an exponential function. In this thesis, not only values but also equally spaced derivatives are tested. Still using same idea of the traditional Prony's method, poles and residues can also be extracted with those values and derivatives. The resultant poles and residues will be used to predict the output waveform in DTA analysis. The benefits brought by the using of derivatives include less simulation steps and less CPU time consuming than the regular constant step simulation. As a matter of fact, the Prony's method can precisely approximate a complicated waveform. Such property can be applied for STA analysis. The Prony's approximation can be used to precisely record an output waveform, which is used as an entry of the look-up table of STA. Since the accuracy of STA analysis relies on the accuracy of the input and output waveform in the look-up table, the accuracy of the Prony's approach is promising.

This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in DTA(Dynamic Timing Analysis) and delay look-up table in STA(Static Timing Analysis). Given some equally spaced output values, the traditional Prony's method can be used to extract poles and residues of a linear system, i.e. to characterize a waveform using an exponential function. In this thesis, not only values but also equally spaced derivatives are tested. Still using same idea of the traditional Prony's method, poles and residues can also be extracted with those values and derivatives. The resultant poles and residues will be used to predict the output waveform in DTA analysis. The benefits brought by the using of derivatives include less simulation steps and less CPU time consuming than the regular constant step simulation. As a matter of fact, the Prony's method can precisely approximate a complicated waveform. Such property can be applied for STA analysis. The Prony's approximation can be used to precisely record an output waveform, which is used as an entry of the look-up table of STA. Since the accuracy of STA analysis relies on the accuracy of the input and output waveform in the look-up table, the accuracy of the Prony's approach is promising.

This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in DTA(Dynamic Timing Analysis) and delay look-up table in STA(Static Timing Analysis). Given some equally spaced output values, the traditional Prony's method can be used to extract poles and residues of a linear system, i.e. to characterize a waveform using an exponential function. In this thesis, not only values but also equally spaced derivatives are tested. Still using same idea of the traditional Prony's method, poles and residues can also be extracted with those values and derivatives. The resultant poles and residues will be used to predict the output waveform in DTA analysis. The benefits brought by the using of derivatives include less simulation steps and less CPU time consuming than the regular constant step simulation. As a matter of fact, the Prony's method can precisely approximate a complicated waveform. Such property can be applied for STA analysis. The Prony's approximation can be used to precisely record an output waveform, which is used as an entry of the look-up table of STA. Since the accuracy of STA analysis relies on the accuracy of the input and output waveform in the look-up table, the accuracy of the Prony's approach is promising.

This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in DTA(Dynamic Timing Analysis) and delay look-up table in STA(Static Timing Analysis). Given some equally spaced output values, the traditional Prony's method can be used to extract poles and residues of a linear system, i.e. to characterize a waveform using an exponential function. In this thesis, not only values but also equally spaced derivatives are tested. Still using same idea of the traditional Prony's method, poles and residues can also be extracted with those values and derivatives. The resultant poles and residues will be used to predict the output waveform in DTA analysis. The benefits brought by the using of derivatives include less simulation steps and less CPU time consuming than the regular constant step simulation. As a matter of fact, the Prony's method can precisely approximate a complicated waveform. Such property can be applied for STA analysis. The Prony's approximation can be used to precisely record an output waveform, which is used as an entry of the look-up table of STA. Since the accuracy of STA analysis relies on the accuracy of the input and output waveform in the look-up table, the accuracy of the Prony's approach is promising.

As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable because high correlations exist between supply voltage and delay. Supply noise analysis has often used a vector-based timing analysis approach. Finding a set of test vectors in vector-based approaches, however, is very expensive, particularly during the design phase, and becomes intractable for larger circuits in DSM technology. In this work, two novel vectorless approaches are described such that increases in circuit delay, because of power supply noise, can be efficiently, quickly estimated. Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less than 2%, and both of my approaches are 67 times faster than the traditional vector-based approach. Also, the results show the importance of considering care-bits, which sensitize the longest paths during the power supply noise analysis.

Modern digital designs require high performance and low cost. In this scenario, timing analysis is an essential step for each phase of the integrated circuit design cycle. To minimize the design turn-around time, the ability to correctly predict the timing behavior of the chip is extremely important. This has resulted in a demand for techniques to perform an accurate timing analysis. A number of existing timing analysis approaches are available. Most of these are pessimistic in nature due because of some inherent inaccuracies in the modeling of the timing behavior of logic gates. Although some techniques use accurate gate delay models, they have only been used to calculate the longest sensitizable delay or the shortest topological path delay for the circuit. In this work, a procedure to and the shortest destabilizing delay, as well as the longest sensitizable delay of a static CMOS circuit is developed. This procedure is also able to determine the exact circuit path as well as the input vector transition for which the shortest destabilizing (or longest sensitizable) delay can be achieved. Over a number of examples, on an average, the minimum destabilizing delay results in an improvement of 24% as compared to the minimum static timing analysis approach. The maximum sensitizable timing analysis results in an improvement of 7% over sensitizable timing analysis with pin-to-output delays. Therefore, the results show that the pessismism in timing analysis can be considerably decreased by using data dependent gate delays for maximum as well as minimum sensitizable timing analysis.

As multi-core systems are becoming more popular in real time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic RAM (DDR DRAM) is highly desirable. Several researchers have proposed predictable memory controllers to provide guaranteed memory access latency. However, the performance of such controllers sharply decreases as DDR devices become faster and the width of memory buses is increased. Therefore, a novel and composable approach is proposed that provides improved latency bounds compared to existing works by explicitly modeling the DRAM state. In particular, this new approach scales better with increasing number of cores and memory speed. Benchmark evaluation results show up to a 45% improvement in the worst case task execution time compared to a competing predictable memory controller for a system with 16 cores.

<p>Autoliv has developed the Night Vision system, which is a safety system for use incars to improve the driver’s situational awareness during night conditions. It is areal-time system that is able to detect pedestrians in the traffic environment andissue warnings when there is a risk of collision. The timing behaviour of programsrunning on real-time systems is vital information when developing and optimisingboth hardware and software. As a part of further developing their Night Visionsystem, Autoliv wanted to examine detailed timing behaviour of a specific part ofthe Night Vision algorithm, namely the Tracking module, which tracks detectedpedestrians. Parallel to this, they also wanted a reliable method to obtain timingdata that would work for other parts of that system as well, or even other applications.</p><p>A preliminary study was conducted in order to determine the most suitable methodof obtaining the timing data desired. This resulted in a measurement-based approachusing software profiling, in which the Tracking module was measured usingvarious input data. The measurements were performed on simulated hardwareusing both a cycle accurate simulator and measurement tools from the systemCPU manufacturer, as well as tools implemented specifically to handle input andoutput data.</p><p>The measurements resulted in large amounts of data used to compile performancestatistics. Using different scenarios in the input data, we were able to obtain timingcharacteristics for several typical situations the system may encounter duringoperation. By manipulating the input data we were also able to observe generalbehaviour and achieve artificially high execution times, which serves as indicationson how the system responds to irregular and unexpected input data.</p><p>The method used for collecting timing information was well suited for this particularproject. It provided the possibility to analyse behavior in a better waythan other, more theoretical, approaches would have. The method is also easilyadaptable to other parts of the Night Vision system, or other systems, with onlyminor adjustments to measurement environment and tools.</p>