As semiconductor technology advances into the nano-scale era and more functional blocks are added into systems on chip (SoC), the interface between circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers are influencing both circuit performance and yield. As a result, design tools need to incorporate new factors. One important source of circuit performance degradation comes from deterministic within-die variation from lithography imperfections and Cu interconnect chemical mechanical polishing (CMP). To determine how these within-die variations impact circuit performance, a new analysis tool is required. Thus a methodology has been proposed to involve layout-dependent within-die variations in static timing analysis. The methodology combines a set of scripts and commercial tools to analyze a full chip. The tool has been applied to analyze delay of ISCAS85 benchmark circuits in the presence of imperfect lithography and CMP variation. Also, this thesis presents a methodology to generate test sets to diagnose the sources of within-die variation. Specifically, a delay fault diagnosis algorithm is developed to link failing signatures to physical mechanisms and to distinguish among different sources of within-die variation. The algorithm relies on layout-dependent timing analysis, path enumeration, test pattern generation, and correlation of pass/fail signatures to diagnose lithography-caused delay faults. The effectiveness in diagnosis is evaluated for ISCAS85 benchmark circuits.

Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this dissertation, we study three challenging issues in delay test: fault modeling, variational delay evaluation and path selection under process variation. Previous research of fault modeling on resistive spot defects, such as resistive opens and bridges in the interconnect, and resistive shorts in devices, lacked an accurate fault model. As a result it was difficult to perform fault simulation and select the best vectors. Conventional methods to compute variational delay under process variation are either slow or inaccurate. On the problem of path selection under process variation, previous approaches either choose too many paths, or missed the path that is necessary to be tested. We present new solutions in this dissertation. A new fault model that clearly and comprehensively expresses the relationship between electrical behaviors and resistive spots is proposed. Then the effect of process variations on path delays is modeled with a linear function and a fast method to compute coefficients of the linear function is also derived. Finally, we present the new path pruning algorithms that efficiently prune unimportant paths for test, and as a result we select as few as possible paths for test while the fault coverage is satisfied. The experimental results show that the new solutions are efficient and accurate.

Autoliv has developed the Night Vision system, which is a safety system for use incars to improve the driver’s situational awareness during night conditions. It is areal-time system that is able to detect pedestrians in the traffic environment andissue warnings when there is a risk of collision. The timing behaviour of programsrunning on real-time systems is vital information when developing and optimisingboth hardware and software. As a part of further developing their Night Visionsystem, Autoliv wanted to examine detailed timing behaviour of a specific part ofthe Night Vision algorithm, namely the Tracking module, which tracks detectedpedestrians. Parallel to this, they also wanted a reliable method to obtain timingdata that would work for other parts of that system as well, or even other applications. A preliminary study was conducted in order to determine the most suitable methodof obtaining the timing data desired. This resulted in a measurement-based approachusing software profiling, in which the Tracking module was measured usingvarious input data. The measurements were performed on simulated hardwareusing both a cycle accurate simulator and measurement tools from the systemCPU manufacturer, as well as tools implemented specifically to handle input andoutput data. The measurements resulted in large amounts of data used to compile performancestatistics. Using different scenarios in the input data, we were able to obtain timingcharacteristics for several typical situations the system may encounter duringoperation. By manipulating the input data we were also able to observe generalbehaviour and achieve artificially high execution times, which serves as indicationson how the system responds to irregular and unexpected input data. The method used for collecting timing information was well suited for this particularproject. It provided the possibility to analyse behavior in a better waythan other, more theoretical, approaches would have. The method is also easilyadaptable to other parts of the Night Vision system, or other systems, with onlyminor adjustments to measurement environment and tools.

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This thesis presents a simulation model for a Control Area Network (CAN) software stack, the Dual FIFO CAN (DFC) stack, and a method for identifying and incorporating the details of the host environment (hardware setup, operating system, etc.) into the implementation of the simulation model in order to achieve a high level of fidelity. The method enable the simulation model to produce more realistic simulation results that are close to real-life experiments of the target system compared to existing commercial and academic simulation tools, which mostly ignore the system details The simulation model is implemented based on the specification documents of the DFC stack as well as knowledge gained from real-life experiments about the DFC stack and its host environment, a dual-core Electric Control Unit (ECU) hardware test bench that runs a Real-Time Operating System (RTOS). Like the actual DFC stack, the simulation model offers features such as dual non-preemptive FIFO transmit queues and TX buffers, and reserved slots in the queues for higher-priority messages. By using the method introduced in this research, the simulation model also offers options, once enabled and configured with proper parameters, for simulating a host environment that has effects on the behaviors of the modeled CAN stack. And these features are not fully available in existing commercial and academic simulation tools. The model provides internal calibration values of the DFC stack as configurable parameters to the user, making it easy to customize the simulation. Configurable calibration values includes the total number of slots in the transmit FIFO queues, number of reserved slots in the queues, transmit-rate thresholds that decide to which transmit queue a message is routed and whether a message is eligible to enter the reserved slots of the queues, and together they determine the queuing behaviors of the DFC stack. The options for simulating a host environment (an ECU on a CAN network in a modern vehicle, for instance) is capable of recreating the timing effects (delays, jitters or other effects due to the processing load, physical limitation and internal implementation) of the target host environment on the simulation results. Both deterministic (constant values, etc.) and/or statistical (probability distributions, etc.) models can be used to configure each single timing effect from the simulated host environment. The simulation model is also automated to transmit a set of customized transmit message (configurable message ID, DLC, period and internal transmission priority) and process simulation results according to the purpose of the simulation (statistical analysis, plots of data, etc). These features make it possible for the simulation model to be used not only to simulate various customized simulation scenarios, but also for different purposes in various stages of the development process, for instance, a pre-experiment simulation run before a test bench experiment to test the correctness of the calibrations and predict the possible outcomes of the experiment, or, simulations for confirmation purposes in order validate the test bench data after the test experiment. The model is compatible with typical modeling, simulation and development environments as it is implemented in MATLAB SimEvents environment, which works with third-party CAN development tools such as Vector CANoe. It is also designed to work with the high-fidelity model of the Vector CAN protocol stack from Whinton (2016). / Thesis / Master of Applied Science (MASc)

As the mobile electronic products development are more and more popular such as mobile phone, digital camera, PDA¡Ketc. Each of company releases variable kind of mobile products, and every portable machine has plenty of functions. A low power consumption design is a significant issue which academics and engineers concern. It would be a major progress if the approach which can drop off the power consumption successfully. The mobile electronic products have more application programs than before and the size of LCD increases continuously, so that the power consumption becomes large. Therefore, expanding the life of battery would be a significant issue. Besides, the process technology has improved day by day, and it would influence the supply voltage be declined. It represents the power management would influence the power consumption of circuit directly. Comparing to drop down the entire IC power consumption and not to influence the performance of IC, the thesis employs the algorithm that searches the Critical Path and embeds the Level Converter Logic into digital circuit. It can offer the proper supply voltage to circuits which do not want to bigger supply voltage for reduce power consumption. However, the process variation (Inter-Die or Intra-Die) may transform the original Critical Path, the Critical Path which searches through the static timing analysis would not correct. To conquer this problem, the thesis provides the statistical approach to analysis timing. It would search Path Sensitivity which is exactly equal to the probability that a path is critical. Finally, the logic gate which is designed by us would replace the UMC 90nm standard cell through Cell-Based.

This dissertation reports on a new methodology to characterize and simulate a standard cell library to be used for statistical static timing analysis. A compact variation-aware timing model for a standard cell in a cell library has been developed. The model incorporates variations in the input waveform and loading, process parameters, and the environment into the cell timing model. Principal component analysis (PCA) has been used to form a compact model of a set of waveforms impacted by these sources of variation. Cell characterization involves determining equations describing how waveforms are transformed by a cell as a function of the input waveforms, process parameters, and the environment. Different versions of factorial designs and Latin hypercube sampling have been explored to model cells, and their complexity and accuracy have been compared. The models have been evaluated by calculating the delay of paths. The results demonstrate improved accuracy in comparison with table-based static timing analysis at comparable computational cost. Our methodology has been expanded to adapt to interconnect dominant circuits by including a resistive-capacitive load model. The results show the feasibility of using the new load model in our methodology. We have explored comprehensive accuracy improvement methods to tune the methodology for the best possible results. The following is a summary of the main contributions of this work to the statistical static timing analysis: (a) accurate waveform modeling for standard cells using statistical waveform models based on principal components; (b) compact performance modeling of standard cells using experimental design statistical techniques; and (c) variation-aware performance modeling of standard cells considering the effect of variation parameters on performance, where variation parameters include loading, waveform shape, process parameters (gate length and threshold voltage of NMOS and PMOS transistors), and environmental parameters (supply voltage and temperature); and (f) extending our methodology to support resistive-capacitive loads to be applicable to interconnect dominant circuits; and (e) classifying the sources of error for our variational waveform model and cell models and introducing of the related accuracy improvement methods; and (f) introducing our fast block-based variation-aware statistical dynamic timing analysis framework and showing that (i) using compiler-compiler techniques, we can generate our timing models, test benches, and data analysis for each circuit, which are compiled to machine-code to reduce the overhead of dynamic timing simulation, and (ii) using the simulation engine, we can perform statistical timing analysis to measure the performance distribution of a circuit using a high-level model for gate delay changes, which can be linked to their parameter variation.

With advances in technology, modern integrated circuits have higher complexities and reduced transistor sizing. In deep sub-micron, the parameter variation-control is difficult and component delays vary from one manufactured chip to another. Therefore, the delays are not discrete values but are a statistical quantity, and statistical evaluation methods have gained traction. Furthermore, fault injection based gate-level fault coverage is non-scalable and statistical estimation methods are preferred. This dissertation focuses on scalable statistical methods to select critical paths in the presence of process variations, and to improve the defect coverage for complex integrated circuits. In particular, we investigate the sensitization probability of a path by a test pattern under statistical delays. Next, we investigate test pattern generation for improving the sensitization probability of a path, selecting critical paths that yield high defect coverage, and scalable method to estimate fault coverage of complex designs using machine learning techniques.

Driven by the need for faster devices and higher transistor densities, technology trends have pushed transistor dimensions into the deep sub-micron regime. This continued scaling, however, has led to many challenges facing digital integrated circuits today. One important challenge is the increased variations in the underlying process and environmental parameters, and the significant impact of this variability on circuit timing and leakage power, making it increasingly difficult to design circuits that achieve a required specification. Given these challenges, there is a need for computer-aided design (CAD) techniques that can predict and analyze circuit performance (timing and leakage) accurately and efficiently in the presence of variability. This thesis presents new techniques for variation-aware timing and leakage analysis that address different aspects of the problem. First, on the timing front, a pre-placement statistical static timing analysis technique is presented. This technique can be applied at an early stage of design, when within-die correlations are still unknown. Next, a general parameterized static timing analysis framework is proposed, which supports a general class of nonlinear delay models and handles both random (process) parameters with arbitrary distributions and non-random (environmental) parameters. Following this, a parameterized static timing analysis technique is presented, which can capture circuit delay exactly at any point in the parameter space. This is enabled by identifying all potentially critical paths in the circuit through novel and efficient pruning algorithms that improve on the state of art both in theoretical complexity and runtime. Also on the timing front, a novel distance-based metric for robustness is proposed. This metric can be used to quantify the susceptibility of parameterized timing quantities to failure, thus enabling designers to fix the nodes with smallest robustness values in order to improve the overall design robustness. Finally, on the leakage front, a statistical technique for early-mode and late-mode leakage estimation is presented. The novelty lies in the random gate concept, which allows for efficient and accurate full-chip leakage estimation. In its simplest form, the leakage estimation reduces to finding the area under a scaled version of the within-die channel length auto-correlation function, which can be done in constant time.

Driven by the need for faster devices and higher transistor densities, technology trends have pushed transistor dimensions into the deep sub-micron regime. This continued scaling, however, has led to many challenges facing digital integrated circuits today. One important challenge is the increased variations in the underlying process and environmental parameters, and the significant impact of this variability on circuit timing and leakage power, making it increasingly difficult to design circuits that achieve a required specification. Given these challenges, there is a need for computer-aided design (CAD) techniques that can predict and analyze circuit performance (timing and leakage) accurately and efficiently in the presence of variability. This thesis presents new techniques for variation-aware timing and leakage analysis that address different aspects of the problem. First, on the timing front, a pre-placement statistical static timing analysis technique is presented. This technique can be applied at an early stage of design, when within-die correlations are still unknown. Next, a general parameterized static timing analysis framework is proposed, which supports a general class of nonlinear delay models and handles both random (process) parameters with arbitrary distributions and non-random (environmental) parameters. Following this, a parameterized static timing analysis technique is presented, which can capture circuit delay exactly at any point in the parameter space. This is enabled by identifying all potentially critical paths in the circuit through novel and efficient pruning algorithms that improve on the state of art both in theoretical complexity and runtime. Also on the timing front, a novel distance-based metric for robustness is proposed. This metric can be used to quantify the susceptibility of parameterized timing quantities to failure, thus enabling designers to fix the nodes with smallest robustness values in order to improve the overall design robustness. Finally, on the leakage front, a statistical technique for early-mode and late-mode leakage estimation is presented. The novelty lies in the random gate concept, which allows for efficient and accurate full-chip leakage estimation. In its simplest form, the leakage estimation reduces to finding the area under a scaled version of the within-die channel length auto-correlation function, which can be done in constant time.