É apresentado um amplificador de potência (PA) com controle digital da potência de saída, operando na banda S de frequência (2,2 GHz). Este PA utiliza um transformador de entrada para reduzir as flutuações dos sinais de terra. Um estágio de excitação oferece uma impedância apropriada para a fonte de entrada e ganho para o próximo estágio. O estágio de controle é usado para melhorar a eficiência do PA, composto por quatro ramos paralelos de chaves, onde os estados (ligado ou desligado) são separadamente ativados por uma palavra de controle de 4 bits. O estágio de saída implementa um amplificador classe E, usando uma topologia cascode para minimizar o estresse de tensão sobre os transistores, permitindo sua utilização sob tensão de alimentação de 3,3 V para se atingir uma potência de saída máxima em torno de 1 W, em um processo CMOS 130 nm, cuja tensão típica de alimentação é 1,2 V. O PA proposto foi projetado em uma tecnologia CMOS 130 nm para RF, ocupa uma área de 1,900 x 0,875 mm2 e os resultados das simulações em leiaute extraído obtidos demonstram uma potência de saída máxima de 28,5 dBm (707 mW), com PAE (Power- Added Efficiency) correspondente de 49,7%, para uma tensão de alimentação de 3,3 V. O controle de 4 bits permite um ajuste dentro da faixa dinâmica da potência de saída entre 13,6 a 28,5 dBm (22,9 a 707 mW), divididos em 15 passos, com o PAE variando de 9,1% a 49,7%. O PA proposto permite redução do consumo de potência quando este não está transmitindo na potência máxima. A potência consumida atinge um mínimo de 0,21Wquando a potência de saída é de 13,6 dBm (22,9 mW) e um máximo de 1,4 W quando a potência de saída é de 28,5 dBm (707 mW), o que representa 1,19 W de economia, aumentando a vida da bateria. A linearidade obtida neste circuito mostrou-se suficiente para atender os requisitos da máscara de emissão de espúrios de um padrão de comunicação com envoltória constante largamente utilizado, apresentando desempenho adequado para atender as especificações dos sistemas de comunicações modernos. / A power amplifier with digital power control useful to S-Band (2.2 GHz) applications and with an output power around 1 W is presented. It uses an input transformer to reduce ground bounce effects. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) is separately activated by a 4-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF CMOS process and the layout has a total area of 1.900 x 0.875 mm2, post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 49.7% under 3.3 V of supply voltage. The 4-bit control allows a total output power dynamic range adjustment of 14.9 dB, divided in 15 steps, with the PAE changing from 9.1% to 49.7%. The proposed PA allows reduce the power consumption when it isn’t transmitting at the maximum output power. Where the power consumption is only 0.21 W when the PA is at the minimum output power level of 13.6 dBm (22.9 mW), which is 1.19 W smaller than the power consumption at full mode (1.4 W), increasing the battery life. The linearity in this circuit meet the emission mask requirements for a widely used communication standard with constant envelope. Post-layout simulation results indicate an overall performance adequate to fulfill the specifications of modern wireless communication systems.

É apresentado um amplificador de potência (PA) com controle digital da potência de saída, operando na banda S de frequência (2,2 GHz). Este PA utiliza um transformador de entrada para reduzir as flutuações dos sinais de terra. Um estágio de excitação oferece uma impedância apropriada para a fonte de entrada e ganho para o próximo estágio. O estágio de controle é usado para melhorar a eficiência do PA, composto por quatro ramos paralelos de chaves, onde os estados (ligado ou desligado) são separadamente ativados por uma palavra de controle de 4 bits. O estágio de saída implementa um amplificador classe E, usando uma topologia cascode para minimizar o estresse de tensão sobre os transistores, permitindo sua utilização sob tensão de alimentação de 3,3 V para se atingir uma potência de saída máxima em torno de 1 W, em um processo CMOS 130 nm, cuja tensão típica de alimentação é 1,2 V. O PA proposto foi projetado em uma tecnologia CMOS 130 nm para RF, ocupa uma área de 1,900 x 0,875 mm2 e os resultados das simulações em leiaute extraído obtidos demonstram uma potência de saída máxima de 28,5 dBm (707 mW), com PAE (Power- Added Efficiency) correspondente de 49,7%, para uma tensão de alimentação de 3,3 V. O controle de 4 bits permite um ajuste dentro da faixa dinâmica da potência de saída entre 13,6 a 28,5 dBm (22,9 a 707 mW), divididos em 15 passos, com o PAE variando de 9,1% a 49,7%. O PA proposto permite redução do consumo de potência quando este não está transmitindo na potência máxima. A potência consumida atinge um mínimo de 0,21Wquando a potência de saída é de 13,6 dBm (22,9 mW) e um máximo de 1,4 W quando a potência de saída é de 28,5 dBm (707 mW), o que representa 1,19 W de economia, aumentando a vida da bateria. A linearidade obtida neste circuito mostrou-se suficiente para atender os requisitos da máscara de emissão de espúrios de um padrão de comunicação com envoltória constante largamente utilizado, apresentando desempenho adequado para atender as especificações dos sistemas de comunicações modernos. / A power amplifier with digital power control useful to S-Band (2.2 GHz) applications and with an output power around 1 W is presented. It uses an input transformer to reduce ground bounce effects. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) is separately activated by a 4-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF CMOS process and the layout has a total area of 1.900 x 0.875 mm2, post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 49.7% under 3.3 V of supply voltage. The 4-bit control allows a total output power dynamic range adjustment of 14.9 dB, divided in 15 steps, with the PAE changing from 9.1% to 49.7%. The proposed PA allows reduce the power consumption when it isn’t transmitting at the maximum output power. Where the power consumption is only 0.21 W when the PA is at the minimum output power level of 13.6 dBm (22.9 mW), which is 1.19 W smaller than the power consumption at full mode (1.4 W), increasing the battery life. The linearity in this circuit meet the emission mask requirements for a widely used communication standard with constant envelope. Post-layout simulation results indicate an overall performance adequate to fulfill the specifications of modern wireless communication systems.

É apresentado um amplificador de potência (PA) com controle digital da potência de saída, operando na banda S de frequência (2,2 GHz). Este PA utiliza um transformador de entrada para reduzir as flutuações dos sinais de terra. Um estágio de excitação oferece uma impedância apropriada para a fonte de entrada e ganho para o próximo estágio. O estágio de controle é usado para melhorar a eficiência do PA, composto por quatro ramos paralelos de chaves, onde os estados (ligado ou desligado) são separadamente ativados por uma palavra de controle de 4 bits. O estágio de saída implementa um amplificador classe E, usando uma topologia cascode para minimizar o estresse de tensão sobre os transistores, permitindo sua utilização sob tensão de alimentação de 3,3 V para se atingir uma potência de saída máxima em torno de 1 W, em um processo CMOS 130 nm, cuja tensão típica de alimentação é 1,2 V. O PA proposto foi projetado em uma tecnologia CMOS 130 nm para RF, ocupa uma área de 1,900 x 0,875 mm2 e os resultados das simulações em leiaute extraído obtidos demonstram uma potência de saída máxima de 28,5 dBm (707 mW), com PAE (Power- Added Efficiency) correspondente de 49,7%, para uma tensão de alimentação de 3,3 V. O controle de 4 bits permite um ajuste dentro da faixa dinâmica da potência de saída entre 13,6 a 28,5 dBm (22,9 a 707 mW), divididos em 15 passos, com o PAE variando de 9,1% a 49,7%. O PA proposto permite redução do consumo de potência quando este não está transmitindo na potência máxima. A potência consumida atinge um mínimo de 0,21Wquando a potência de saída é de 13,6 dBm (22,9 mW) e um máximo de 1,4 W quando a potência de saída é de 28,5 dBm (707 mW), o que representa 1,19 W de economia, aumentando a vida da bateria. A linearidade obtida neste circuito mostrou-se suficiente para atender os requisitos da máscara de emissão de espúrios de um padrão de comunicação com envoltória constante largamente utilizado, apresentando desempenho adequado para atender as especificações dos sistemas de comunicações modernos. / A power amplifier with digital power control useful to S-Band (2.2 GHz) applications and with an output power around 1 W is presented. It uses an input transformer to reduce ground bounce effects. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) is separately activated by a 4-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF CMOS process and the layout has a total area of 1.900 x 0.875 mm2, post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 49.7% under 3.3 V of supply voltage. The 4-bit control allows a total output power dynamic range adjustment of 14.9 dB, divided in 15 steps, with the PAE changing from 9.1% to 49.7%. The proposed PA allows reduce the power consumption when it isn’t transmitting at the maximum output power. Where the power consumption is only 0.21 W when the PA is at the minimum output power level of 13.6 dBm (22.9 mW), which is 1.19 W smaller than the power consumption at full mode (1.4 W), increasing the battery life. The linearity in this circuit meet the emission mask requirements for a widely used communication standard with constant envelope. Post-layout simulation results indicate an overall performance adequate to fulfill the specifications of modern wireless communication systems.

This thesis presents the design and development of two switching amplifiers used to drive the so-called smart material actuators. Different from conventional circuits, a smart material actuator is ordinarily a highly capacitive load. Its capacitance is non-linear and its strain is hysteretic with respect to its electrical control signal. This actuator's reactive load property usually causes a large portion of reactive power circulating between the power amplifier and the driven actuator, thus reduces the circuit efficiency in a linear power amplifier scenario. In this thesis, a switching amplifier design based on the PWM technique is proposed to develop a highly efficient power amplifier, and peak current mode control is proposed to reduce the actuator's hysteretic behavior. Since the low frequency current loop gain tends to be low due to the circuit's capacitive load, average current mode control is further proposed to boost the low frequency current loop gain and improve the amplifier's low frequency performance. Both of the circuits have been verified by prototype design and their experimental measurement results are given. / Master of Science

Les travaux de thèse présentés dans ce manuscrit portent sur l’alimentation d’actionneurs de type piézo-électrique qui seront placés sur la partie tournante d’une perceuse. Ces actionneurs possèdent un comportement capacitif et sont habituellement alimentés par des systèmes linéaires. Une étude de dimensionnement et de conception a été menée sur différents amplificateurs à découpage qui peuvent fournir, dans un repère fixe, un signal de puissance sinusoïdal à fréquence variable dans les meilleures conditions possibles (rendement et THD). Ensuite, un système pouvant transférer l’énergie sans contact à l’actionneur piézo-électrique placé sur un repère tournant a été analysé. Cela a été possible grâce à l’utilisation des systèmes à induction, c’est-à-dire, par couplage magnétique à travers un transformateur tournant présentant un entrefer. Trois types de systèmes de transfert d’énergie sans contact ont été étudiés : l’un qui travaille à la fréquence de l’actionneur [50-500 Hz] et deux autres basés sur des stratégies de résonance permettant ainsi de diminuer les dimensions du coupleur magnétique. Pour cela, la modélisation tant magnétique qu’électrique a été effectuée dans les trois systèmes.Un prototype d’onduleur en pont complet fournissant jusqu’à 680 VAR a été réalisé. Ce dernier est placé en amont d’un coupleur magnétique basse fréquence transférant 1,75 kVAR à l’actionneur piézo-électrique en rotation. Les résultats obtenus en pratique ont montré la pertinence du travail de dimensionnement et conception. / Placed on the rotating part of a drilling system. These actuators have a capacitive behavior and are usually supplied by linear systems. In this case, the design and the sizing of different switching amplifiers that provide, in a fixed frame, a sinusoidal power signal with modular frequency in the best possible conditions (efficiency and THD) have been made. Then, a contactless power system for piezoelectric actuators placed in a rotating frame was analyzed. This was possible thanks to the use of induction systems through a rotating transformer with an air gap. Three types of contactless systems were studied. The first one works at modular low frequencies [50-500 Hz] and the other two use resonant strategies in order to reduce transformer’s size. For this, both magnetic and electrical modeling was performed in the three cases.A full-bridge inverter prototype that can deliver up to 680 VAR and a low frequency contactless energy transfer system of 1.75 kVAR that supplies the piezoelectric actuator at rotating frame have been made. Experimental results showed satisfactory results and proved the system feasibility.

This diploma thesis deals with digital audio amplifier with universal inputs and its design. The first part describes modulation and audio formats for audio electronics. The thesis contain design of a block diagram of the digital audio amplifier and describes the requirements for functional blocks. As a basic device for audio signal processing was choosen integrated circuit STA326. The thesis continue with circuits design for each blocks with a description of their principles. The next section describes the construction and firmware for microcontroller. The last part of this diploma thesis is targeted on the presentation of the measured parameters of the amplifier. The conclusion summarizes the results that have been achieved and advantages and disadvantages of the digital audio amplifier prototype.

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance.