Gene networks can be modeled by piecewise-linear (PL) switching systems of differential equations, called Glass networks after their originator. Networks of interacting genes that regulate each other may have complicated interactions. From a `systems biology' point of view, it would be useful to know what types of dynamical behavior are possible for certain classes of network interaction structure. A useful way to describe the activity of this network symbolically is to represent it as a directed graph on a hypercube of dimension $n$ where $n$ is the number of elements in the network. Our work here is considering this problem backwards, i.e. we consider different types of cycles on the $n$-cube and show that there exist parameters, consistent with the directed graph on the hypercube, such that a periodic orbit exists. For any simple cycle on the $n$-cube with a non-branching vertex, we prove by construction that it is possible to have a stable periodic orbit passing through the corresponding orthants for some sets of focal points $F$ in Glass networks. When the simple cycle on the $n$-cube doesn't have a non-branching vertex, a structural principle is given to determine whether it is possible to have a periodic orbit for some focal points. Using a similar construction idea, we prove that for self-intersecting cycles where the vertices revisited on the cycle are not adjacent, there exist Glass networks which have a periodic orbit passing through the corresponding orthants of the cycle. For figure-8 patterns with more than one common vertex, we obtain results on the form of the return map (Poincar{\'e} map) with respect to how the images of the returning cones of the 2 component cycle intersect the returning cone themselves. Some of these allow complex behaviors.

A scheduling algorithm has the primary role in implementing the quality of service guaranteed to each flow by managing buffer space and selecting which packet to send next with a fair share of network. In this thesis, some scheduling algorithms for packet switching networks are studied. For evaluating their delay, jitter and throughput performances, a discrete event simulator has been developed. It has been seen that fair scheduling provides, fair allocation of bandwidth, lower delay for sources using less than their full share of bandwidth and protection from ill-behaved resources.

This term project deals with the functionality of Spanning Tree protocols, especially the Rapid Spanning Tree Protocol, and the Multiple Spanning Tree Protocol. The primary usage of spanning tree protocols is the prevention of loops within the data link layer, the prevention of a broadcast storm, and also dealing with redundancy in the network. Moreover, the project contains the description of configuration of these protocols on Cisco devices. The main goal of this thesis is to implement the Multiple Spanning Tree protocol into INET framework within the OMNeT++ simulation system. Then, the implemented solution is tested and it's functionality is compared with the referential behavior in a Cisco network.

Ultra narrow-band filters and the use of two loops in a cascade configuration dominate current clock conditioners based on phase-locked-loop (PLL) schemes. Since a PLL exhibits a low-pass transfer function with respect to the reference clock, the noise performance at very close-to-carrier offset frequencies is still determined by the input signal. Although better cleaning can be achieved with extremely narrow loops, an ultra low cut-off frequency could not be selected since the stability of the configuration deteriorates as the filter bandwidth is reduced. This fact suggests that a full-spectrum clock conditioning is not possible using traditional PLL architectures, and an alternative scheme is necessary to attenuate the very-close-to-carrier phase noise (PN). In addition, ultra-narrow loop filters can compromise on-chip integration because of the large size capacitors needed when chosen as passive. Input signal attenuation with relaxed bandwidth requirements becomes the main aspect that a comprehensive clock cleaner must address to effectively regenerate a reference signal. This dissertation describes the Band-Reject Nested-PLL (BRN-PLL) scheme, a modified PLL-based architecture that provides an effective signal cleaning procedure by introducing a notch in the input transfer function through inner and outer loops and a high-pass filter (HPF). This modified response attenuates the reference-signal PN and reduces the size of the loop-filter capacitors substantially. Ultra narrow loops are no longer required because the notch size is related to the system bandwidth. The associated transfer function for the constitutive blocks (phase detectors and local oscillators) show that the output close-to-carrier and far-from-carrier PN sections are mainly dominated by the noise from the inner-PLL phase detector (PD) and local oscillator (LO) located in the outer loop, respectively. The inner-PLL PD transfer function maintains a low-pass characteristic with a passband gain inversely proportional to the PD gain becoming the main contribution around the carrier signal. On the other hand, the PN around the transition frequency is determined mainly by the reference and the inner-PLL LO. Their noise contributions to the output will depend on the associated passband local maxima, which is located at the BRN-PLL transition frequency. Hence, in this region, the inner-PLL LO is selected so that its effect can be held below that of the outer-PLL PD. The BRN-PLL can use a high-Q MEMS-based VCO to further improve the transition region of the output PN profile and an LC-VCO as outer-PLL LO to reduce the noise floor of the output signal. In particular, two tuning mechanisms are explored for the MEMS-VCO: series tuning using varactors and phase shifting of a resonator operating in nonlinear regime. Both schemes are implemented to generate a tunable oscillator with no PN-performance degradation.