The power consumption of smart camera in car black box varies significantly between light load and heavy load. The high efficiency voltage regulator is necessary in prolong the life of smart camera battery. Since the smart camera only recording the video when car is driving, the most time of the smart camera works in the sleep mode. Hence the light load efficiency is important in this application, however, conventional buck converter usually have high efficiency at heavy load but poor efficiency at light load. To increase the light load efficiency of buck converter, this research continues Yeago's two phase buck converter with optimum phase selection control and Zhao's two mode buck converter to further improve the light load efficiency for the target application. With 5V input voltage and 1.2V output voltage, the proposed two-mode synchronous buck converter can supply the load power from 12mW to 1.44W. To improve the light load efficiency of conventional buck converter, the proposed design applied Wei's baby buck concept to provide another light load power stage to reduce the switching loss and driving loss at light load. Then, the variable frequency ripple-based constant on-time control with discontinuous conduction mode (DCM) in light load is applied to the baby-buck mode to reduce the switching frequency to further reduce the switching loss. Also, the baby-buck mode uses the synchronous buck topology to remove the diode in asynchronous converter to increase the efficiency at light load. Finally, a sensorless mode selector remove the sensing resistor in power stage to increase the efficiency for entire load range, especially for the heavy load. The mode selector can select the optimum mode for different load condition, and the opposite mode would completely shut down to save the loss. The proposed design is implement in CMOS 0.25um technology. The proposed monolithic buck converter which include the power stage of heavy buck mode, baby-buck mode and the controller is fabricated. The measurement result shows the close loop efficiency varies from 70%-83% toward the entire load range. / Master of Science

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As laptop mobile users expect more application features and long battery life, the processor current has to increase to response the demanding while the voltage has to decease to save the power loss. Therefore, it is necessary for a system designer to improve the efficiency of the voltage regulator converter (VRC) for the processor. Laptop processor architecture is more complicated than desktop because of different mode operations and their transitions. The laptop processor runs at different voltage levels for each operation mode to save the battery life. Therefore, the VRC needs to supply the correct and stable voltage to the processor. In this thesis, an analysis of power loss is derived to estimate the efficiency and switching frequency, three widely current sensing methods are discussed, two methods to compensate for the thermal resistance in loss less current sense methods are proposed, the tolerance of load line base on the component's tolerance in the converter is analyzed, the equation to estimate the output capacitance is derived, and the small signal analysis of multiphase synchronous buck converter with the droop current loop is derived. A hardware prototype was implemented base on 4-phase synchronous buck topology to provide high efficiency and lower cost solution. The results of load line meets the Intel specification in different modes of operation, provides the best transient responses, and meets the specification during the load transient. The control loop lab measurement is also matched with the analysis and simulation. / Master of Science

This thesis presents an analytical approach using Root-Loci method for designing optimum passive series RC snubbers for continuous-current synchronous buck switch mode power supply (SMPS). Synchronous buck SMPS is the most popular power converter topology found in modern consumer electronics. It offers relatively good efficiency to target the high-current and low-voltage requirements while it is also relatively inexpensive to implement. Passive series RC snubbers are simple, efficient and cost-effective open-loop equalizer circuit for synchronous buck SMPS. Its purpose is to control and to balance between the rate of rise and the overshoots of transient switching waveform in order to optimize efficiency and reliability Existing methods of RC snubber design are solely based on second-order approximation. It is investigated in this research that this approximation is highly inaccurate in SMPS applications because higher order equivalent models are required for the load path of the SMPS. The results using the RC snubbers obtained from existing method are shown to be unsatisfactory without correlation to the calculations and simulations based on second-order approximation. Optimum RC values obtained using Root-Loci approach presented in this thesis are shown to correlate to both Spice simulation and lab measurements.

M. Tech. (Engineering: Electrical, Department Electronic Engineering, Faculty of Engineering and Technology), Vaal University of Technology, / “If we think oil is a problem now, just wait 20 years. It’ll be a nightmare.” — Jeremy Rifkin, Foundation of Economic Trends, Washington, D.C., August 2003. This statement harmonises with the reality that human civilisation faces today. As a result, humankind has been forced to look for alternatives to fossil fuels. Among possible solutions, fuel cell (FC) technology has received a lot of attention because of its potential to generate clean energy. Fuel cells have the advantage that they can be used in remote telecommunication sites with no grid connectivity as the majority of telecommunication equipment operates from a DC voltage supply. Power plants based on phosphoric acid fuel cell (PAFC) have been installed worldwide supplying urban areas, shopping centres and medical facilities with electricity, heat and hot water. Although these are facts regarding large scale power plants for on-site use, portable units have been explored as well. Like any other fuel cell, the PAFC output power is highly unregulated leading to a drastic drop in the output voltage with changing load value. Therefore, various DC–DC converter topologies with a wide range of input voltages can be used to regulate the fuel cell voltage to a required DC load. An interleaved synchronous buck converter intended for efficiently stepping down the energy generated by a PAFC was designed and developed. The design is based on the National Semiconductor LM5119 IC. A LM5119 evaluation board was redesigned to meet the requirements for the application. The measurements were performed and it was found that the converter achieved the expectations. The results showed that the converter efficiently stepped down a wide range of input voltages (22 to 46 V) to a regulated 13.8 V while achieving a 93 percent efficiency. The conclusions reached and recommendations for future research are presented. / Telkom Centre of Excellence, TFMC, M-Tech, THRIP.

This thesis presents an analytical approach using Root-Loci method for designing optimum passive series RC snubbers for continuous-current synchronous buck switch mode power supply (SMPS). Synchronous buck SMPS is the most popular power converter topology found in modern consumer electronics. It offers relatively good efficiency to target the high-current and low-voltage requirements while it is also relatively inexpensive to implement. Passive series RC snubbers are simple, efficient and cost-effective open-loop equalizer circuit for synchronous buck SMPS. Its purpose is to control and to balance between the rate of rise and the overshoots of transient switching waveform in order to optimize efficiency and reliability Existing methods of RC snubber design are solely based on second-order approximation. It is investigated in this research that this approximation is highly inaccurate in SMPS applications because higher order equivalent models are required for the load path of the SMPS. The results using the RC snubbers obtained from existing method are shown to be unsatisfactory without correlation to the calculations and simulations based on second-order approximation. Optimum RC values obtained using Root-Loci approach presented in this thesis are shown to correlate to both Spice simulation and lab measurements.

This report is a study of the effects of a commercial 0.13[mu] process and automotive temperature corners on a synchronous DC-DC buck converter design. The basics of switching converters will be explored with an emphasis on voltage-mode controlled feedback. A Type-III compensation network is designed using transfer function analysis to compensate for the inherent double pole introduced by an LC network. The output of the compensation network will drive a pulse width modulation comparator to vary the duty cycle of the high-side PMOS and low-side NMOS transistor switches. After the synchronous buck converter design was complete, the effect of process and temperature on efficiency, output voltage ripple, inductor peak to peak current, and output voltage load response was examined. / text

Power consumption of smart cameras varies significantly between sleep mode and active mode, and a smart camera operates in sleep mode for 80 — 90% of time for typical use. To prolong the battery life of smart cameras, it is essential to increase the power converter efficiency for light load, while being able to manage heavy load. The power stage of traditional buck converter is optimized for maximum load, at the cost of light-load efficiency. Wei proposed a multiphase buck converter incorporating the baby-buck concept and optimum number of phases (ONP) control. This thesis research investigated Wei's multiphase buck converter to improve the light-load efficiency for smart cameras as the target application. The proposed two-phase buck converter aims to provide power for microprocessors of smart cameras. The input voltage of the converter is 5 V DC, and the output voltage is 1.2 V DC with power dissipation range of 25 mA (30 mW) for light load and 833 mA (1 W) for heavy load. Three methods are considered to improve light-load efficiency: adopting baby-buck concept, adapting ONP control for low-power range, and implementing a pulse frequency modulation (PFM) control scheme with discontinuous conduction mode (DCM) to lower switching frequency. The first method is to adopt the baby-buck concept through power stage design of each phase to optimize efficiency for a specific load range. The baby-buck phase is optimized for light load and the heavy-load phase is designed to handle the processors maximum power consumption. The second method performs phase selection from sensed load current information. Rather than have all phases active for heavy-load as in ONP control, optimum phase selection (OPS) control is introduced to adaptively select between phases based on load current. Due to low-power constraints, OPS is more efficient for the medium to heavy-load range. The transition between phases due to load change is also investigated. The third and final method implements PFM control with DCM to lower switching frequency and reduce switching and driving losses under light load. PFM is accomplished with a constant on-time (COT) valley current mode controller, which uses the inductor current information and output voltage to generate switching signals for both the top and bottom switches. The baby-buck phase enters DCM to lower switching frequency under very light load, while the heavy-load phase remains in continuous conduction mode (CCM) throughout its load range. The proposed two-phase buck converter is designed and prototyped using discrete components. Efficiency of the two-phase converter and a power loss breakdown for each block in the control scheme were measured. The efficiency ranges from 64% to 81% for light load ranging of 30 mW to 200 mW, and the efficiency ranges from 81% to 88% for heavy load ranging from 200 mW to 1 W. The majority loss is due to controllers, which are responsible for 37 % (8.6 mW) for light load of 60 mW and for 10.9 % (9 mW) for heavy load of 600 mW. The gate driver loss is considerable for heavy load of 600 mW, consuming 11.9% (9.8mW). The converter has a 10 mV overshoot voltage for a load step-down from 225 mA to 25 mA, and it has 65 mV overshoot voltage for a load step-up from 25 mA to 225 mA. Although, a fair comparison is difficult due to use of discrete parts for OPS control, the proposed converter shows reasonably good efficiency and performance. / Master of Science

The role played by power converting circuits is extremely important to almost any electronic system built today. Circuits that use converters of any type depend on power that is consistent in form and reliable in order to properly function. In addition, today's demands require more efficient use of energy, from large stationary systems such as power plants all the way down to small mobile devices such as laptops and cell phones. This places a need to reduce any losses to a minimum. The power conversion circuitry in a system is a very good place to reduce a large amount of unnecessary loss. This can be done using circuit topologies that are low loss in nature. For low loss and high performance, soft switching topologies have offered solutions in some cases. Also, limited study has been performed on device aging effects on switching mode power converting circuits. The impact of this effect on a converter's overall efficiency is theoretically known but with little experimental evidence in support. In this thesis, non-isolated buck type switching converters will be the main focus. This type of power conversion is widely used in many systems for DC to DC voltage step down. Newer methods and topologies to raise converter power efficiency are discussed, including a new synchronous ZVT topology . Also, a study has been performed on device aging effects on converter efficiency. Various scenarios of voltage conversion, switching frequency, and circuit components as well as other conditions have been considered. Experimental testing has been performed in both cases, ZVT's benefits and device aging effects, the results of which are discussed as well.

In order to provide the means to set up a control theory lab experiment involving position control of a brushed DC motor with current feedback, a pulse-width modulated motor controller was designed. The output voltage is controlled by an analog reference signal and the magnitude of the output current and voltage are measured and output. These inputs and outputs are connected to a DAQ I/O-unit such that the lab experiment can be implemented digitally. In addition, defining equations for the whole system were derived. Comparison between measurements and model showed it possible to use the current as feedback if low-pass filtered and the angular displacement controlled over a small angular interval.