The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope. / The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.

The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope. / The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.

<p>The technical evolution during the past decade have escalated the use of electronic devices, which are more common today than ever before. The market is still growing rapidly and will continue to do so. The reason for this is the increased demand for devices with integrated circuits. In addition to the increased volume of production, the chips are also becoming more complex which is also reflected in the requirements of the chip design process.</p><p>An advanced chip that combines several different hardware modules (cores) to form a complete system is called a System-on-Chip (SoC). It is of great importance that these chips work according to expectation, although it can be difficult to guarantee. The purpose of SoC testing is to verify correct behaviour as well as for diagnosis and debug.</p><p>Complex systems lead to more and bigger tests which lead to increased test data volume and test time. This results in a higher test cost and many methods are proposed to remedy this situation.</p><p>This report proposes a method that minimises fail result data with a real-time compression component embedded on the chip. The compressed fail results can be saved on-chip and retrieved when needed instead of during the test.</p><p>Furthermore this method will facilitate debug and diagnosis of SoCs. A mask buffer is used to give the opportunity of choosing exactly which cycles, pins or bits that are relevant. All other result bits are masked and ignored.</p><p>The results are satisfying, the data is compressed to a much smaller size which is easier to store on-chip. The method is simple, fast and loss-less.</p>

The technical evolution during the past decade have escalated the use of electronic devices, which are more common today than ever before. The market is still growing rapidly and will continue to do so. The reason for this is the increased demand for devices with integrated circuits. In addition to the increased volume of production, the chips are also becoming more complex which is also reflected in the requirements of the chip design process. An advanced chip that combines several different hardware modules (cores) to form a complete system is called a System-on-Chip (SoC). It is of great importance that these chips work according to expectation, although it can be difficult to guarantee. The purpose of SoC testing is to verify correct behaviour as well as for diagnosis and debug. Complex systems lead to more and bigger tests which lead to increased test data volume and test time. This results in a higher test cost and many methods are proposed to remedy this situation. This report proposes a method that minimises fail result data with a real-time compression component embedded on the chip. The compressed fail results can be saved on-chip and retrieved when needed instead of during the test. Furthermore this method will facilitate debug and diagnosis of SoCs. A mask buffer is used to give the opportunity of choosing exactly which cycles, pins or bits that are relevant. All other result bits are masked and ignored. The results are satisfying, the data is compressed to a much smaller size which is easier to store on-chip. The method is simple, fast and loss-less.

No description available.

Les communications entre les applications réseaux sont régies par un ensemble de règles regroupées sous forme de protocoles. Les messages protocolaires sont gérés par une couche de l’application réseau connue comme étant la couche de support protocolaire. Cette couche peut être de nature logicielle, matérielle ou conjointe. Cette couche se trouve à la frontière entre le coeur de l’application et le monde extérieur. A ce titre, elle représente un composant névralgique de l’application. Les performances globales de l’application sont ainsi directement liées aux performances de la couche de support protocolaire associée.Le processus de développement de ces couches consiste à traduire une spécification du protocole, écrite dans un langage de haut niveau tel que ABNF dans un langage bas niveau, logiciel ou matériel. Avec l’avènement des systèmes embarqués, de plus en plus de systèmes sur puce proposent l’utilisation de ressources matérielles afin d’accroître les performances des applicatifs. Néanmoins, peu de processus de développement de couches de support protocolaire tirent parti de ces ressources, en raison notamment de l’expertise nécessaire dans ce domaine.Cette thèse propose une approche générative conjointe logicielle-matérielle au développement du support protocolaire d’applications réseaux, pour améliorer leur performance tout en restant ergonomique pour le développeur de l’application. Notre approche est basée sur l’exploitation d’un langage dédié, appellé Zebra pour générer les différents composants logiciels et matériels formant la couche de support. L’expertise nécessaire est déportée dans l’utilisation du langage Zebra et les composants matériels générés permettent d’accroître les performances de l’application.Les contributions de cette thèse sont les suivantes : Nous avons effectué une analyse des protocoles et applications réseaux. Cette analyse nous a permis d’identifier les composants pour lesquels il est possible d’obtenir des gains de performances.Nous avons conçu et exploité un langage dédié, Zebra, permettant de décrire les différentes entités de la couche de support protocolaire et générant les éléments logiciels et matériels la composant. Nous avons construit un système sur puce exécutant un système d’exploitation Linux afin d’étayer notre approche. Nous avons conçu des accélérateurs matériels déployables pour différents protocoles réseaux sur ce système et pilotables par les applicatifs. Afin de rendre l’accès aux accélérateurs matériels transparent pour les applications réseaux, nous avons développé un intergiciel gérant l’ensemble de ces accès. Cet intergiciel permet à plusieurs applications et/ou à plusieurs clients d’une même application d’utiliser les accélérateurs pour le traitement des messages protocolaires. Nous avons évalué les performances de notre approche dans des conditions réelles. Nous avons comparé ces performances à celles de couches de supports faisant référence dans le domaine. Nous avons constaté un gain de performance conséquent pour l’approche que nous proposons. / Communications between network applications is achieved by using rulesets known as protocols. Protocol messages are managed by the application layer known as the protocol parsing layer or protocol handling layer. Protocol parsers are coded in software, in hardware or based on a co-design approach. They represent the interface between the application logic and the outside world. Thus, they are critical components of network applications. Global performances of network applications are directly linked to the performances of their protocol parser layers.Developping protocol parsers consists of translating protocol specifications, written in a high level language such as ABNF towards low level software or hardware code. As the use of embedded systems is growing, hardware ressources become more and more available to applications on systems on chip (SoC). Nonetheless, developping a network application that uses hardware ressources is challenging, requiring not only expertise in hardware design, but also a knowledge of the protocols involved and an understanding of low-level network programming.This thesis proposes a generative hardware-software co-design based approach to the developpement of network protocol message parsers, to improve their performances without increasing the expertise the developper may need. Our approach is based on a dedicated language, called Zebra, that generates both hardware and software elements that compose protocol parsers. The necessary expertise is deported in the use of the Zebra language and the generated hardware components permit to improve global performances.The contributions of this thesis are as follows : We provide an analysis of network protocols and applications. This analysis allows us to detect the elements which performances can be improved using hardware ressources. We present the domain specific language Zebra to describe protocol handling layers. Software and hardware components are then generated according to Zebra specifications. We have built a SoC running a Linux operating system to assess our approach.We have designed hardware accelerators for different network protocols that are deployed and driven by applications. To increase sharing of parsing units between several tasks, we have developped a middleware that seamlessly manages all the accesses to the hardware components. The Zebra middleware allows several clients to access the ressources of a hardware accelerator. We have conducted several set of experiments in real conditions. We have compared the performances of our approach with the performances of well-knownprotocol handling layers. We observe that protocol handling layers baded on our approach are more efficient that existing approaches.

L'intégration d'un plus grand nombre de fonctions sur des circuits intégrés plus rapides à chaque nouvelle génération. Malheureusement, elles ont rendu la tâche des concepteurs plus difficile, avec notamment la montée de la puissance consommée et des temps de propagation des signaux à travers la puce. La distribution de l'horloge, assurant le synchronisme des opérations du circuit, en est l'élément le plus symptomatique. La génération distribuée de l'horloge apparaît comme une alternative aux solutions classiques. Elle repose sur la mise en place d'un réseau de N oscillateurs géographiquement distribués sur l'ensemble de la puce. Chaque oscillateur génère localement une horloge pour la zone de la puce dans laquelle il se trouve. La phase d'une horloge est accordée sur celle de ces proches voisines. Ainsi, l'horloge n'a plus à parcourir de long chemin. Toutefois, les performances du circuit d'horloge sont liées, non pas à un, mais à N oscillateurs évoluant dans un environnement hostile (variations de l'alimentation, de la température, etc.). Aussi, les travaux de cette thèse portent sur la conception d'un oscillateur contrôlé numériquement. Plus précisément, notre problématique est : " Comment concevoir un DCO (Digitally Controlled Oscillator) robuste soumis à l'environnement hostile d'un SoC en technologie CMOS submicronique ? ". Pour répondre à cette question, nous proposons, dans un premier temps, la modélisation d'une topologie d'oscillateur contrôlé numériquement ; le but étant de déterminer sa pertinence quant à notre application d'horlogerie. Comme cette dernière est émergente, il n'y a à l'heure actuelle aucune théorie la caractérisant. A travers notre analyse, nous mettons en évidence ses faiblesses et la nécessité de lui adjoindre des circuits de protection. De ce fait, les performances du circuit d'horloge ne sont plus seulement dépendantes de l'oscillateur, mais aussi des dispositifs mis en place pour le protéger des agressions des circuits environnants. Ce constat a motivé le développement d'une alternative qui ne serait pas soumise aux mêmes contraintes. Nous proposons finalement un oscillateur contrôlé numériquement robuste à la fois contre les variations de l'alimentation et de la température. Cet oscillateur est conçu à partir de blocs analogiques connus et bien décrits par la littérature. Pour limiter l'influence de la tension d'alimentation et de la température à laquelle évolue l'oscillateur, nous tirons profit des effets de canal court propres aux technologies submicroniques.

Modern technologies are growing and Voice over Internet Protocol (VoIP) technology is able to function in heterogeneous networks. VoIP gained wide popularity because it offers cheap calling rates compared to traditional telephone system and the number of VoIP subscribers has increased significantly in recent years. End users need reliable and acceptable call quality in real time communication with best Quality of Service (QoS). Server complexity is increasing to handle all client requests simultaneously and needs huge processing power. VoIP Servers will increase processing power but the engineering tradeoff needs to be considered e.g. increasing hardware will increase hardware complexity, energy consumption, network management, space requirement and overall system complexity. Modern System-on-Chip (SoC) uses multiple core technology to resolve the complexity of hardware computation. With enterprises needing to reduce overall costs while simultaneously improving call setup time, the amalgamation of VoIP with SoC can play a major role in the business market. The proposed VoIP Server model with multiple processing capabilities embedded in it is tailored for multicore hardware to achieve the required result. The model uses SystemC-2.2.0 and TLM-2.0 as a platform and consists of three main modules. TLM is built on top of SystemC in an overlay architectural fashion. SystemC provides a bridge between software and hardware co-design and increases HW &amp; SW productivity, driven by fast concurrent programming in real time. The proposed multicore VoIP Server model implements a round robin algorithm to distribute transactions between cores and clients via Load Balancer. Primary focus of the multicore model is the processing of call setup time delays on a VoIP Server. Experiments were performed using OpenSIP Server to measure Session Initiation Protocol (SIP) messages and call setup time processing delays. Simulations were performed at the KTH Ferlin system and based on the theoretical measurements from the OpenSIP Server experiments. Results of the proposed multicore VoIP Server model shows improvement in the processing of call setup time delays.

In the last two decades, Field Programmable Gate Arrays (FPGAs) have been rapidly developed from simple “glue-logic” to a powerful platform capable of implementing a System on Chip (SoC). Modern FPGAs achieve not only the high performance compared with General Purpose Processors (GPPs), thanks to hardware parallelism and dedication, but also better programming flexibility, in comparison to Application Specific Integrated Circuits (ASICs). Moreover, the hardware programming flexibility of FPGAs is further harnessed for both performance and manipulability, which makes Dynamic Partial Reconfiguration (DPR) possible. DPR allows a part or parts of a circuit to be reconfigured at run-time, without interrupting the rest of the chip’s operation. As a result, hardware resources can be more efficiently exploited since the chip resources can be reused by swapping in or out hardware tasks to or from the chip in a time-multiplexed fashion. In addition, DPR improves fault tolerance against transient errors and permanent damage, such as Single Event Upsets (SEUs) can be mitigated by reconfiguring the FPGA to avoid error accumulation. Furthermore, power and heat can be reduced by removing finished or idle tasks from the chip. For all these reasons above, DPR has significantly promoted Reconfigurable Computing (RC) and has become a very hot topic. However, since hardware integration is increasing at an exponential rate, and applications are becoming more complex with the growth of user demands, highlevel application design and low-level hardware implementation are increasingly separated and layered. As a consequence, users can obtain little advantage from DPR without the support of system-level middleware. To bridge the gap between the high-level application and the low-level hardware implementation, this thesis presents the important contributions towards a Reliable, Reconfigurable and Real-Time Operating System (R3TOS), which facilitates the user exploitation of DPR from the application level, by managing the complex hardware in the background. In R3TOS, hardware tasks behave just like software tasks, which can be created, scheduled, and mapped to different computing resources on the fly. The novel contributions of this work are: 1) a novel implementation of an efficient task scheduler and allocator; 2) implementation of a novel real-time scheduling algorithm (FAEDF) and two efficacious allocating algorithms (EAC and EVC), which schedule tasks in real-time and circumvent emerging faults while maintaining more compact empty areas. 3) Design and implementation of a faulttolerant microprocessor by harnessing the existing FPGA resources, such as Error Correction Code (ECC) and configuration primitives. 4) A novel symmetric multiprocessing (SMP)-based architectures that supports shared memory programing interface. 5) Two demonstrations of the integrated system, including a) the K-Nearest Neighbour classifier, which is a non-parametric classification algorithm widely used in various fields of data mining; and b) pairwise sequence alignment, namely the Smith Waterman algorithm, used for identifying similarities between two biological sequences. R3TOS gives considerably higher flexibility to support scalable multi-user, multitasking applications, whereby resources can be dynamically managed in respect of user requirements and hardware availability. Benefiting from this, not only the hardware resources can be more efficiently used, but also the system performance can be significantly increased. Results show that the scheduling and allocating efficiencies have been improved up to 2x, and the overall system performance is further improved by ~2.5x. Future work includes the development of Network on Chip (NoC), which is expected to further increase the communication throughput; as well as the standardization and automation of our system design, which will be carried out in line with the enablement of other high-level synthesis tools, to allow application developers to benefit from the system in a more efficient manner.

Os atuais sistemas eletrônicos desenvolvidos na forma de SoCs (Sistemas-sobre-Silício) são caracterizados pelo incremento de informação crítica que é capturada, armazenada e processada. Com a introdução dos SoCs nos sistemas distribuídos que promovem o compartilhamento dos recursos, a segurança vem se transformando num requisito de projeto extremamente importante. Os atuais SoCs são alvo de ataques. O desafio consiste em projetar um SoC seguro que satisfaça os requisitos de segurança e desempenho, próprios para cada aplicação. A estrutura de comunicação está se tornando o coração do SoC. Esta possui um impacto significativo no desempenho do sistema. A inclusão de serviços de segurança na estrutura de comunicação é vantajosa devido à sua capacidade de: 1) monitorar a informação transmitida; 2) detectar violações; 3) bloquear ataques; e 4) fornecer informações para diagnóstico e ativação de mecanismos de recuperação e defesa. O presente trabalho propõe a implementação do conceito de QoSS (Qualidade do Serviço de Segurança) no projeto da estrutura de comunicação baseada em redes intrachip (NoCs, Network-on-Chip). QoSS permite a inclusão da segurança como uma dimensão de QoS (Quality-of-Sevice), admitindo a existência de diferentes níveis de proteção. A adoção do QoSS no projeto das NoCs permite a exploração do espaço de projeto das NoCs levando em consideração o compromisso entre a segurança do sistema e o desempenho do sistema. A inclusão do QoSS na NoC é realizada através de uma metodologia que inclui 5 etapas: definição, descrição, implementação, avaliação e otimização. Como resultado é obtido um conjunto de NoCsQoSS que satisfazem os requisitos de segurança e desempenho do sistema. Criamos neste trabalho o ambiente de simulação APOLLO que fornece suporte na rápida exploração do espaço de soluções a partir de modelos SystemC-TLM do SoC. Neste trabalho, apresentamos três estudos de caso que utilizam a nossa metodologia de projeto de NoCs com QoSS na implementação de políticas de segurança estática e dinâmica. Os serviços de segurança de controle de acesso e autenticação foram implementados de duas formas: na interface da rede e no roteador. Realizamos a avaliação da eficácia e eficiência das NoCs resultantes sob diferentes condições de ataques e de tráfego, resultado da variação topológica do tráfego, natureza e tipo de tráfego. Mostramos que a implementação da segurança no roteador é mais eficiente que a implementação na interface da rede em termos de latência e potência sob todas as diferentes condições de tráfego. Porém, a utilização na interface permite a inclusão das características da segurança na NoC de uma maneira mais simples. Desta forma para sistemas complexos a implementação na interface é vantajosa. / As embedded electronic systems are pervading our lives, security is emerging as an extremely important design requirement. Due to the increasing complexity, intrinsic embedded constraints and strict requirements, security and performance are considered challenging tasks. Most of the current electronic systems embedded in a SoC (System-on-Chip) are used to capture, store, manipulate and access sensitive data and perform several critical functions without security guarantee. The challenge is to provide SoC security that allows a trustworthy system that meets the security and performance requirements. As security requirements vary dramatically for different applications, differentiated security services are necessary. The SoC communication structure is becoming the heart of the SoC. It has a significant impact on the overall system performance. The security services integration at the communication structure take advantage of its wide system visibility and critical role in enabling the system operation. It is able to: 1) monitor data transfer; 2) detect attacks; 3) block attacks; and 4) supply information for trigger suitable recovery mechanisms. This work proposes the implementation of the QoSS (Quality-of-Security-Service) concept at the NoC-based communication structure design. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. In contrast with previous works, the different security levels deployment allow a best trade-of the system security and performance requirements. The QoSS integration is carried out trough a 5 step methodology: definition, description, implementation, evaluation and optimization. As a result a set of NoCs-QoSS that satisfies the security and performance requirements are obtained. We use the framework APOLLO that integrates a set of tools, allowing the fast exploration of the huge NoC design space. In this work we present 2 study cases that uses our methodology in order to design a NoC-QoSS that supports static and a dynamic security policies and also satisfies the security and performance requirements. Two security services: Access Control and authentication are implemented at the NoC interface and at the NoC router. The final configurations are evaluated under different traffic and attack conditions. We show that the security implementation at the router is latency and power consumption efficient that the implementation at the network interface under all the traffic conditions. However, the security implementation at the network interface allows the integration of the security characteristics in a simpler way.