Os atuais sistemas eletrônicos desenvolvidos na forma de SoCs (Sistemas-sobre-Silício) são caracterizados pelo incremento de informação crítica que é capturada, armazenada e processada. Com a introdução dos SoCs nos sistemas distribuídos que promovem o compartilhamento dos recursos, a segurança vem se transformando num requisito de projeto extremamente importante. Os atuais SoCs são alvo de ataques. O desafio consiste em projetar um SoC seguro que satisfaça os requisitos de segurança e desempenho, próprios para cada aplicação. A estrutura de comunicação está se tornando o coração do SoC. Esta possui um impacto significativo no desempenho do sistema. A inclusão de serviços de segurança na estrutura de comunicação é vantajosa devido à sua capacidade de: 1) monitorar a informação transmitida; 2) detectar violações; 3) bloquear ataques; e 4) fornecer informações para diagnóstico e ativação de mecanismos de recuperação e defesa. O presente trabalho propõe a implementação do conceito de QoSS (Qualidade do Serviço de Segurança) no projeto da estrutura de comunicação baseada em redes intrachip (NoCs, Network-on-Chip). QoSS permite a inclusão da segurança como uma dimensão de QoS (Quality-of-Sevice), admitindo a existência de diferentes níveis de proteção. A adoção do QoSS no projeto das NoCs permite a exploração do espaço de projeto das NoCs levando em consideração o compromisso entre a segurança do sistema e o desempenho do sistema. A inclusão do QoSS na NoC é realizada através de uma metodologia que inclui 5 etapas: definição, descrição, implementação, avaliação e otimização. Como resultado é obtido um conjunto de NoCsQoSS que satisfazem os requisitos de segurança e desempenho do sistema. Criamos neste trabalho o ambiente de simulação APOLLO que fornece suporte na rápida exploração do espaço de soluções a partir de modelos SystemC-TLM do SoC. Neste trabalho, apresentamos três estudos de caso que utilizam a nossa metodologia de projeto de NoCs com QoSS na implementação de políticas de segurança estática e dinâmica. Os serviços de segurança de controle de acesso e autenticação foram implementados de duas formas: na interface da rede e no roteador. Realizamos a avaliação da eficácia e eficiência das NoCs resultantes sob diferentes condições de ataques e de tráfego, resultado da variação topológica do tráfego, natureza e tipo de tráfego. Mostramos que a implementação da segurança no roteador é mais eficiente que a implementação na interface da rede em termos de latência e potência sob todas as diferentes condições de tráfego. Porém, a utilização na interface permite a inclusão das características da segurança na NoC de uma maneira mais simples. Desta forma para sistemas complexos a implementação na interface é vantajosa. / As embedded electronic systems are pervading our lives, security is emerging as an extremely important design requirement. Due to the increasing complexity, intrinsic embedded constraints and strict requirements, security and performance are considered challenging tasks. Most of the current electronic systems embedded in a SoC (System-on-Chip) are used to capture, store, manipulate and access sensitive data and perform several critical functions without security guarantee. The challenge is to provide SoC security that allows a trustworthy system that meets the security and performance requirements. As security requirements vary dramatically for different applications, differentiated security services are necessary. The SoC communication structure is becoming the heart of the SoC. It has a significant impact on the overall system performance. The security services integration at the communication structure take advantage of its wide system visibility and critical role in enabling the system operation. It is able to: 1) monitor data transfer; 2) detect attacks; 3) block attacks; and 4) supply information for trigger suitable recovery mechanisms. This work proposes the implementation of the QoSS (Quality-of-Security-Service) concept at the NoC-based communication structure design. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. In contrast with previous works, the different security levels deployment allow a best trade-of the system security and performance requirements. The QoSS integration is carried out trough a 5 step methodology: definition, description, implementation, evaluation and optimization. As a result a set of NoCs-QoSS that satisfies the security and performance requirements are obtained. We use the framework APOLLO that integrates a set of tools, allowing the fast exploration of the huge NoC design space. In this work we present 2 study cases that uses our methodology in order to design a NoC-QoSS that supports static and a dynamic security policies and also satisfies the security and performance requirements. Two security services: Access Control and authentication are implemented at the NoC interface and at the NoC router. The final configurations are evaluated under different traffic and attack conditions. We show that the security implementation at the router is latency and power consumption efficient that the implementation at the network interface under all the traffic conditions. However, the security implementation at the network interface allows the integration of the security characteristics in a simpler way.

Jusqu'à présent, le test de circuits intégrés et des systèmes au niveau wafer est basé sur un contact physique entre l'équipement de test et les circuits sur le wafer. Cette méthode basée sur le contact est limitée par plusieurs facteurs, tels que le nombre de circuits testés en parallèle, la réduction de la taille et de l'espacement entre les plots de contact, le nombre de contact avant que les plots soient endommagés, le coût des opérations de test, entre autres. Pour résoudre ces problèmes, nous proposons une nouvelle approche de test basée sur la communication sans fil entre le testeur et les circuits à tester (DUT). Pour cela, un Wireless Test Control Bloc (WTCB) est ajouté à chaque DUT sur le wafer comme une interface sans fil entre le testeur et les structures de test internes du DUT. Ce WTCB intègre une pile protocolaire de communication pour gérer la communication avec le testeur, et un Test Control Bloc (TCB) pour gérer l'application de test au niveau DUT. Profitant d'une transmission sans fil, le testeur peut diffuser les données de test à tous les DUT sur le wafer , maximisant le test simultané et réduisant donc le temps de test. En outre, notre architecture de WTCB permet une comparaison locale de la réponse de DUT avec la réponse correcte attendue par le testeur. En effectuant cette comparaison dans le WTCB du DUT, le testeur recueille de chaque DUT 1 seul bit comme résultat de la comparaison, au lieu d'une réponse complète, conduisant à un test sans fil plus rapide qui réduit le temps d'essai. Le WTCB a été mis en oeuvre sur FPGA, et une épreuve de test sans fil d'un circuit réel a été réalisée, prouvant la conception efficace de notre WTCB, et soulignant le potentiel de notre méthode de test sans fil, où elle peut être étendue et utilisée pour des applications de test in situ à distance. / So far, the test of integrated circuits and systems at wafer level relies on a physical contact between the test equipment and the devices under test on the wafer. This contact-based method is limited by several factors, such as the number of devices tested in parallel, the reduction of the size and the pitch of the bond pads, the number of touchdowns before bond pads are damaged, the cost of the test operations, among others. To solve these issues, we propose a novel test approach and architecture based on wireless communication between the tester and the devices under test (DUT). For that, a Wireless Test Control Block (WTCB) is added to every DUT on the wafer as a wireless interface between the tester and the internal test structures of the DUT. This WTCB embeds a communication protocol stack to manage the communication with the tester, and a Test Control Block to manage the test application at DUT level. Taking advantage of a wireless transmission, the tester can broadcast the test data to all DUT on the wafer in one path, maximizing the concurrent test, and reducing therefore the test time. Moreover, our WTCB architecture allows a local comparison of the DUT response with the correct response expected by the tester. By performing this comparison in the WTCB of the DUT, the tester collects from every DUT its 1-bit comparison result instead of a complete response, leading to a faster wireless test and extremely reduced test time. The WTCB has been implemented on FPGA, and a successful wireless test of a real circuit was performed, proving the efficient design of our WTCB, and highlighting the potential of our wireless test method, where it can be extended and used to perform a remote in-situ test.

De nos jours la conception des IP (IP: Intellectual Property) peut bénéficier de nouvelles techniques de vérification symbolique: abstraction de donnée et analyse statique formelle. Nous pensons qu'il est nécessaire de séparer clairement le Contrôle des Données avant toute vérification automatique. Nous avons proposé une définition du contrôle qui repose sur l'idée intuitive qu'il a un impact sur le séquencement de données. Autour de cette idée, le travail a consisté à s'appuyer sur la sémantique des opérateurs booléens et proposer une extension qui exprime cette notion deséquencement. Ceci nous a mené à la conclusion que la séparation parfaite du contrôle et des données est illusoire car les calculs dépendent trop de la représentation syntaxique. Pour atteindre notre objectif, nous nous sommes alors basés sur la connaissance fournie par le concepteur: séparation a priori des entrées contrôle et des entrées données. De cela, nous avons proposé un algorithme de slicing pour partitionner le modèle. Une abstraction fut alors obtenue dans le cas où le contrôle est bien indépendant des données. Pour accélérer les simulations, nous avons remplacé le traitement de données, défini au niveau bit par un modèle d'exécution fonctionnel, tout en gardant inchangé la partie contrôle. Ce modèle intègre des aspects temporels qui permet de se greffer sur des outils de model checking. Nous introduisons la notion de significativité support des données intentionnelles dans les modèles IP. La significativité est utilisée pour représenter des dépendances de données booléennes en vue de vérifier formellement et statiquement les lots de données. Nous proposons plusieurs approximations qui mettent en oeuvre cette nouvelle notion.

Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.

<p>Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.</p>

Bei der Entwickelung von System-on-Chip (SoC) Debuggern ist es leider hinreichend oft erforderlich den Debugger selbst auf mögliche Fehler zu untersuchen. Da alle ernstzunehmenden Debugger konstruktionsbedingt selbst ein eingebettetes System darstellen, erwächst die Notwendigkeit eine einfache und sicher kontrollierbare Diagnose-Hardware zu entwerfen, welche den Zugang zur Funktionsweise des Debuggers über seine Ausgänge erschließt. Derzeitig ist der Test Access Port (TAP nach IEEE 1149.1-Standard) für viele Integratoren die Grundlage für den Zugriff auf ihre instanzierte Hardware. Selbst in forschungsorientierten Multi- Core System-on-Chip Architekturen wie dem ARM11MP der Firma ARM wird dieses Verfahren noch immer eingesetzt. In unserem Beitrag möchten wir ein Spezialwerkzeug zur Analyse des TAPKommunikationsprotokolles vorstellen, welches den Einsatz teurer Analysetechnik (Logik- Analysatoren) unnötig werden lässt und darüber hinaus eine komfortable, weitergehende Unterstützung für Multi-Core-Systeme bietet. Aufbauend auf der Problematik der Abtastung und Erfassung der Signalzustände am TAP mittels FPGA wird auf die verschiedenen Visualisierungs- und Analyseaspekte der TAPProtokollphasen in einer Multi-Core-Prozessor-Zielsystemumgebung eingegangen. Die hier vorgestellte Lösung ist im Rahmen eines FuE-Verbundprojektes enstanden. Das Vorhaben wird im Rahmen der Technologieförderung mit Mitteln des Europäischen Fonds für regionale Entwicklung (EFRE) 2000-2006 und mit Mitteln des Freistaates Sachsen gefördert.

L'utilisation de la troisième dimension peut entraîner une réduction significative de la puissance et de la latence moyenne du trafic dans les réseaux sur puce (Network-on-Chip). La technologie des vias à travers le substrat (ou Through-Silicon Via) est la technologie la plus prometteuse pour l'intégration 3D, car elle offre des liens verticaux courts qui remédient au problème des longs fils dans les NoCs-2D. Les TSVs sont cependant énormes et les processus de fabrication sont immatures, ce qui réduit le rendement des systèmes sur puce à base de NoC-3D. Par conséquent, l'idée de réseaux sur puce 3D partiellement connectés verticalement a été introduite pour bénéficier de la technologie 3D tout en conservant un haut rendement. En outre, de tels réseaux sont flexibles, car le nombre, l'emplacement et l'affectation des liens verticaux dans chaque couche peuvent être décidés en fonction des exigences de l'application. Cependant, ce type de réseaux pose un certain nombre de défis : Le routage est le problème majeur, car l'élimination de certains liens verticaux fait que l'on ne peut utiliser les algorithmes classiques qui suivent l'ordre des dimensions. Pour répondre à cette question nous expliquons et évaluons un algorithme de routage déterministe appelé “Elevator First”, qui garanti d'une part que si un chemin existe, alors on le trouve, et que d'autre part il n'y aura pas d'interblocages. Fondamentalement, la performance du NoC est affecté par a) la micro architecture des routeurs et b) l'architecture d'interconnexion. L'architecture du routeur a un effet significatif sur la performance du NoC, à cause de la latence qu'il induit. Nous présentons la conception et la mise en œuvre de la micro-architecture d'un routeur à faible latence implantant​​l'algorithme de routage Elevator First, qui consomme une quantité raisonnable de surface et de puissance. Du point de vue de l'architecture, le nombre et le placement des liens verticaux ont un rôle important dans la performance des réseaux 3D partiellement connectés verticalement, car ils affectent le nombre moyen de sauts et le taux d'utilisation des FIFOs dans le réseau. En outre, l'affectation des liens verticaux vers les routeurs qui n'ont pas de ports vers le haut ou/et le bas est une question importante qui influe fortement sur les performances. Par conséquent, l'exploration architecturale des réseaux sur puce 3D partiellement connectés verticalement est importante. Nous définissons, étudions et évaluons des paramètres qui décrivent le comportement du réseau, de manière à déterminer le placement et l'affectation des liens verticaux dans les couches de manière simple et efficace. Nous proposons une méthode d'estimation quadratique visantà anticiper le seuil de saturation basée sur ces paramètres. / Utilization of the third dimension can lead to a significant reduction in power and average hop-count in Networks- on-Chip (NoC). TSV technology, as the most promising technology in 3D integration, offers short and fast vertical links which copes with the long wire problem in 2D NoCs. Nonetheless, TSVs are huge and their manufacturing process is still immature, which reduces the yield of 3D NoC based SoC. Therefore, Vertically-Partially-Connected 3D-NoC has been introduced to benefit from both 3D technology and high yield. Moreover, Vertically-Partially-Connected 3D-NoC is flexible, due to the fact that the number, placement, and assignment of the vertical links in each layer can be decided based on the limitations and requirements of the design. However, there are challenges to present a feasible and high-performance Vertically-Partially-Connected Mesh-based 3D-NoC due to the removed vertical links between the layers. This thesis addresses the challenges of Vertically-Partially-Connected Mesh-based 3D-NoC: Routing is the major problem of the Vertically-Partially-Connected 3D-NoC. Since some vertical links are removed, some of the routers do not have up or/and down ports. Therefore, there should be a path to send a packet to upper or lower layer which obviously has to be determined by a routing algorithm. The suggested paths should not cause deadlock through the network. To cope with this problem we explain and evaluate a deadlock- and livelock-free routing algorithm called Elevator First. Fundamentally, the NoC performance is affected by both 1) micro-architecture of routers and 2) architecture of interconnection. The router architecture has a significant effect on the performance of NoC, as it is a part of transportation delay. Therefore, the simplicity and efficiency of the design of NoC router micro architecture are the critical issues, especially in Vertically-Partially-Connected 3D-NoC which has already suffered from high average latency due to some removed vertical links. Therefore, we present the design and implementation the micro-architecture of a router which not only exactly and quickly transfers the packets based on the Elevator First routing algorithm, but it also consumes a reasonable amount of area and power. From the architecture point of view, the number and placement of vertical links have a key role in the performance of the Vertically-Partially-Connected Mesh-based 3D-NoC, since they affect the average hop-count and link and buffer utilization in the network. Furthermore, the assignment of the vertical links to the routers which do not have up or/and down port(s) is an important issue which influences the performance of the 3D routers. Therefore, the architectural exploration of Vertically-Partially-Connected Mesh-based 3D-NoC is both important and non-trivial. We define, study, and evaluate the parameters which describe the behavior of the network. The parameters can be helpful to place and assign the vertical links in the layers effectively. Finally, we propose a quadratic-based estimation method to anticipate the saturation threshold of the network's average latency.

In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two chips, one FPGA and a processor, to an internal bus implemented on only one chip, System on Chip. The work is based on measurements made in real time in Xilinx’s development tools on different buses, AXI4 and AXI4-Light connected to AXI3. The port that is used is FPGA’s own GP-port. Besides measuring the time of transactions also physical aspects have been investigated in this project: space, costs and time. Based on those criteria a comparison to the original construction was made to determine which benefits that can be achieved. The work has shown a number of results that are in comparison with the original construction. The System on Chip has turned out to be a better solution in most cases. When using the AXI4-Light-bus the benefits were not as obvious. Cosmic radiation, temperature or humidity are beyond the scope of this investigation. In the work the hypothetic deductive method has been used to prove that the System on Chip is faster than the original design. In this method three statements must be set up against each other; one statement that ought to be true, one statement that is a contradiction and a conclusion of what is proved. The pre-study pointed out that the System on Chip is a faster solution than the original construction. The method is useful since it proves that the pre-study is comparable to the measured results. / I detta examensarbete har undersökningar gjorts för att fastställa vilka vinster som går att göra genom att byta en internbuss mellan två chip, en FPGA och en processor, mot en intern buss implementerat på ett enda chip, System on Chip. Arbetet bygger på mätningar gjorda i realtid i Xilinx utvecklingsverktyg på olika bussar, AXI4 och AXI4‑Lite som är kopplade internt mot AXI3. Den port som används är FPGAs egen GP‑port. Förutom att mäta överföringshastigheterna, har även fysiska aspekter som utrymme, kostnader och utvecklingstid undersökts. Utifrån dessa kriterier har en jämförelse gjorts med den befintliga konstruktionen för att fastställa vilka vinster som går att uppnå. Arbetet har resulterat i ett antal resultat som är ställda mot de förutsättningar som fanns i den ursprungliga lösningen. I de flesta fall visar resultatet att ett System on Chip är en bättre lösning. De fall som var tveksamma var vid viss typ av överföring med AXI4‑Lite bussen. I arbetet har inte undersökning av kosmisk strålning, temperatur eller luftfuktighet betraktas. I arbetet med att försöka att bevisa att ett System on Chip är snabbare än den ursprungliga uppsättningen har utvecklingsmetoden hypotetisk deduktiv använts. Denna metod bygger på att man från början sätter upp ett påstående, som man förutsätter är sant, följt av en konjunktion, som inte får inträffa, för att slutligen dra en slutsats, som konstaterar fakta. Eftersom fakta som lästes in i början av arbetet pekade på att ett System on Chip var en snabbare och billigare lösning kändes metoden användbar. Under arbetets gång har det visat sig vara en bra metod som också ger ett resultat där sannolikheten för att det är en snabbare lösning ökar. Däremot säger inte metoden att det är helt säkert att den i alla situationer är bättre, vilket kan ändras om man använder andra förutsättningar eller tar med andra aspekter.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.

<p>Network on Chip is a scalable and flexible communication infrastructure for the design of core based System on Chip. Communication performance of a NoC depends heavily on the routing algorithm. Deterministic and adaptive distributed routing algorithms have been advocated in all the current NoC architectural proposals. In this thesis we make a case for the use of source routing for NoCs, especially for regular topologies like mesh. The advantages of source routing include in-order packet delivery; faster and simpler router design; and possibility of mixing non-minimal paths in a mainly minimal routing. We propose a method to compute paths for various communications in such a way that traffic congestion is avoided while ensuring deadlock free routing. We also propose an efficient scheme to encode the paths.</p><p>We developed a tool in Matlab that computes paths for source routing for both general and application specific communications. Depending upon the type of traffic, this tool computes paths for source routing by selecting best routing algorithm out of many routing algorithms. The tool uses a constructive path improvement algorithm to compute paths that give more uniform link load distribution. It also generates different types of traffics. We also developed a simulator capable of simulating source routing for mesh topology NoC. The experiments and simulations which we performed were successful and the results show that the advantages of source routing especially lower packet latency more than compensate its disadvantages. The results also demonstrate that source routing can be a good routing candidate for practical core based SoCs design using network on chip communication infrastructure.</p>