Radio frequency interference is an ever growing problem in the wireless community. This dissertation presents methods to reduce interference for vehicular multi-antenna devices. This document is organized into two parts: the main chapters and the appendices. The main chapters present research conducted primarily by the author. These deserve the reader's primary attention. The appendices showcase contributions made by the author serving in a supporting role to projects led by others and/or do not fit the vehicular theme. These should receive secondary attention. The main chapter contributions are summarized as follows. A device was created that provides over 105 dB of transmit to receive isolation in a full duplex printed circuit board radio. This technology can improve the effective range of vehicular radar systems and increase the bandwidth of full duplex communication schemes for vehicles. The technologies involved are compatible with existing circuit board topologies and are mindful of the size and weight requirements for vehicular use. This isolation performance pushes the state of the art for printed circuit board designs and provides greater capability for these kinds of devices. Recent system on chip computing architectures are opening new pathways for integrating phased array technologies into a single chip. The computer engineering required to configure these devices is beyond the capabilities of many vehicle systems engineers, inviting the author to use one to implement a 16 antenna adaptive beamformer for GPS. The adaptive beamformer can combat multipath bounces and malicious spoofing from ground sources. The high rate analog conversion architecture eliminates the local oscillator distribution to simplify the analog front end to an active antenna. This allows vehicular phased arrays to use smaller footprints and suggests that multi-antenna beamforming devices may be easier to deploy on small to midsized vehicles. Bench tests of the beamformer indicate it can adapt to the environment and increase the received signal strength suggesting it can improve GPS quality for active deployments. The bank of subspace projection beamformers is a popular choice for mitigating interference in digital phased array receivers. A method was discovered that maps that matrix operator into a circuit topology that is simple to implement in an analog circuit and cancels across the entire bandwidth simultaneously. This can offload computational interference mitigation from the signal processor while still allowing secondary multi-pixel digital beamforming downstream. This beamformer was analytically connected to the body of phased array literature and studied to estimate practical error bounds and design methods of calibration.

Modern technologies are growing and Voice over Internet Protocol (VoIP) technology is able to function in heterogeneous networks. VoIP gained wide popularity because it offers cheap calling rates compared to traditional telephone system and the number of VoIP subscribers has increased significantly in recent years. End users need reliable and acceptable call quality in real time communication with best Quality of Service (QoS). Server complexity is increasing to handle all client requests simultaneously and needs huge processing power. VoIP Servers will increase processing power but the engineering tradeoff needs to be considered e.g. increasing hardware will increase hardware complexity, energy consumption, network management, space requirement and overall system complexity. Modern System-on-Chip (SoC) uses multiple core technology to resolve the complexity of hardware computation. With enterprises needing to reduce overall costs while simultaneously improving call setup time, the amalgamation of VoIP with SoC can play a major role in the business market. The proposed VoIP Server model with multiple processing capabilities embedded in it is tailored for multicore hardware to achieve the required result. The model uses SystemC-2.2.0 and TLM-2.0 as a platform and consists of three main modules. TLM is built on top of SystemC in an overlay architectural fashion. SystemC provides a bridge between software and hardware co-design and increases HW & SW productivity, driven by fast concurrent programming in real time. The proposed multicore VoIP Server model implements a round robin algorithm to distribute transactions between cores and clients via Load Balancer. Primary focus of the multicore model is the processing of call setup time delays on a VoIP Server. Experiments were performed using OpenSIP Server to measure Session Initiation Protocol (SIP) messages and call setup time processing delays. Simulations were performed at the KTH Ferlin system and based on the theoretical measurements from the OpenSIP Server experiments. Results of the proposed multicore VoIP Server model shows improvement in the processing of call setup time delays.

The work presented in this thesis aims at validating an original multicriteria performances estimation tool, NESSIE, dedicated to the prediction of performances to accelerate the design of electronic embedded systems. <p><p>This tool has been developed in a previous thesis to cope with the limitations of existing design tools and offers a new solution to face the growing complexity of the current applications and electronic platforms and the multiple constraints they are subjected to. <p><p>More precisely, the goal of the tool is to propose a flexible framework targeting embedded systems in a generic way and enable a fast exploration of the design space based on the estimation of user-defined criteria and a joint hierarchical representation of the application and the platform.<p><p>In this context, the purpose of the thesis is to put the original framework NESSIE to the test to analyze if it is indeed useful and able to solve current design problems. Hence, the dissertation presents :<p><p>- A study of the State-of-the-Art related to the existing design tools. I propose a classification of these tools and compare them based on typical criteria. This substantial survey completes the State-of-the-Art done in the previous work. This study shows that the NESSIE framework offers solutions to the limitations of these tools.<p>- The framework of our original mapping tool and its calculation engine. Through this presentation, I highlight the main ingredients of the tool and explain the implemented methodology.<p>- Two external case studies that have been chosen to validate NESSIE and that are the core of the thesis. These case studies propose two different design problems (a reconfigurable processor, ADRES, applied to a matrix multiplication kernel and a 3D stacking MPSoC problem applied to a video decoder) and show the ability of our tool to target different applications and platforms. <p><p>The validation is performed based on the comparison of a multi-criteria estimation of the performances for a significant amount of solutions, between NESSIE and the external design flow. In particular, I discuss the prediction capability of NESSIE and the accuracy of the estimation. <p><p>-The study is completed, for each case study, by a quantification of the modeling time and the design time in both flows, in order to analyze the gain achieved by our tool used upstream from the classical tool chain compared to the existing design flow alone. <p><p><p>The results showed that NESSIE is able to predict with a high degree of accuracy the solutions that are the best candidates for the design in the lower design flows. Moreover, in both case studies, modeled respectively at a low and higher abstraction level, I obtained a significant gain in the design time. <p><p>However, I also identified limitations that impact the modeling time and could prevent an efficient use of the tool for more complex problems. <p><p>To cope with these issues, I end up by proposing several improvements of the framework and give perspectives to further develop the tool. / Doctorat en Sciences de l'ingénieur / info:eu-repo/semantics/nonPublished

The work presented in this thesis targets the analysis and implementation of multi-criteria performance prediction methods for System-on-Chips (SoC).<p>These new SoC architectures offer the opportunity to integrate complete heterogeneous systems into a single chip and can be used to design battery powered handhelds, security critical systems, consumer electronics devices, etc. However, this variety in terms of application usually comes with a lot of different performance objectives like power consumption, yield, design cost, production cost, silicon area and many others. These performance requirements are often very difficult to meet together so that SoC design usually relies on making the right design choices and finding the best performance compromises.<p>In parallel with this architectural paradigm shift, new Very Deep Submicron (VDSM) silicon processes have more and more impact on the performances and deeply modify the way a VLSI system is designed even at the first stages of a design flow.<p>In such a context where many new technological and system related variables enter the game, early exploration of the impact of design choices becomes crucial to estimate the performance of the system to design and reduce its time-to-market.<p>In this context, this thesis presents: <p>- A study of state-of-the-art tools and methods used to estimate the performances of VLSI systems and an original classification based on several features and concepts that they use. Based on this comparison, we highlight their weaknesses and lacks to identify new opportunities in performance prediction.<p>- The definition of new concepts to enable the automatic exploration of large design spaces based on flexible performance criteria and degrees of freedom representing design choices.<p>- The implementation of a couple of two new tools of our own:<p>- Nessie, a tool enabling hierarchical representation of an application along with its platform and automatically performs the mapping and the estimation of their performance.<p>-Yeti, a C++ library enabling the defintion and value estimation of closed-formed expressions and table-based relations. It provides the user with input and model sensitivity analysis capability, simulation scripting, run-time building and automatic plotting of the results. Additionally, Yeti can work in standalone mode to provide the user with an independent framework for model estimation and analysis.<p><p>To demonstrate the use and interest of these tools, we provide in this thesis several case studies whose results are discussed and compared with the literature.<p>Using Yeti, we successfully reproduced the results of a model estimating multi-core computation power and extended them thanks to the representation flexibility of our tool.<p>We also built several models from the ground up to help the dimensioning of interconnect links and clock frequency optimization.<p>Thanks to Nessie, we were able to reproduce the NoC power consumption results of an H.264/AVC decoding application running on a multicore platform. These results were then extended to the case of a 3D die stacked architecture and the performance benefits are then discussed.<p>We end up by highlighting the advantages of our technique and discuss future opportunities for performance prediction tools to explore. / Doctorat en Sciences de l'ingénieur / info:eu-repo/semantics/nonPublished

Depuis quelques années, les systèmes embarqués n’ont pas cessé d’évoluer. Cette évolution a conduit à des circuits de plus en plus complexes pouvant comporter plusieurs centaines de processeurs sur une même puce.Si la progression des techniques de fabrication des systèmes intégrés, a permis l’amélioration des performances de ces derniers en terme de temps et de capacité de traitement, elle a malheureusement amené une nouvelle contrainte de conception. En effet, cette nouvelle génération de systèmes consomme plus d’énergie et nécessite donc la prise en compte, pendant la phase de conception, des caractéristiques énergétiques dans le but de trouver le meilleur compromis (performance / énergie). Des études montrent qu’une estimation précoce de la consommation – i.e. au niveau comportemental – permet une meilleure diminution de l’énergie consommée par le système.L’outil EDPE (Early Design Power Estimation), objet de cette thèse, propose en réponse à ce besoin, une procédure permettant la caractérisation énergétique précoce d’une architecture de type MPSoC (MultiProcessor System on Chip) dans la phase de prototypage virtuel en System C. EDEP s’appuie sur des modèles de consommation par composant pour en déduire l’énergie dissipée par le système global lorsque le système est simulé au niveau CABA(Cycle Accurate Byte Accurate) ou encore TLM (Transaction Level Model). Les modèles proposés par EDPE, ont été intégrés dans la bibliothèque de prototypage virtuel SoClib. Ainsi, pendant la phase d’exploration architecturale, le concepteur dispose en plus des caractéristiques temporelles et spatiales de son circuit, d’une estimation précise de sa consommation énergétique.L’élaboration de modèles de consommation pour les différents composants matériels d’un système, à l’aide d’EDPE, est simple, homogène et facilement généralisable.Les résultats obtenus montrent la capacité d’EDPE à prédire la consommation énergétique de différentes applications logicielles déployées sur une même architecture matérielle de manière précise et rapide. / Technological trends towards high-level integration combined with the increasing operating frequencies, made embedded systems design become more and more complex.The increase in number of computing resources in integrated circuit (IC) led toover-constrained systems.In fact, SoC (System on Chip) designers must reduce overall system costs, including board space, power consumption and development time.Although many researches have developed methodologies to deal with the emerging requirements of IC design, few of these focused on the power consumption constraint.While the highest accuracy is achieved at the lowest level, estimation time increases significantly when we move down to lower levels.Early power estimation is interesting since it allows to widely explore the architectural design space during the system level partitioning and to early adjust architectural design choices.EDPE estimates power consumption at the system levels and especially CABA (Cycle Accurate Bit Accurate) and TLM (Transaction Level Modelling) levels.The EDPE have been integrated into SoCLib library.The main goal of EDPE (Early Design Power Estimation) is to compare the power consumption of different design partitioning alternatives and chooses the best trade-off power/ performance.Experimental results show that EDPE (Early Design Power Estimation) method provides fast, yet accurate, early power estimation for MPSoCs (MultiprocessorSystem on Chip).EDPE uses few parameters per hardware components and is based on homogeneous and easy characterization method.EDPE is easily generalized to any virtual prototyping library.

Intrinsic evolution of reconfigurable hardware is sought to solve computational problems using the intrinsic processing behavior of System-on-Chip (SoC) platforms. SoC devices combine capabilities of analog and digital embedded components within a reconfigurable fabric under software control. A new technique is developed for these fabrics that leverages the digital resources' enhanced accuracy and signal refinement capability to improve circuit performance of the analog resources' which are providing low power processing and high computation rates. In particular, Differential Digital Correction (DDC) is developed utilizing an error metric computed from the evolved analog circuit to reconfigure the digital fabric thereby enhancing precision of analog computations. The approach developed herein, Cascaded Digital Refinement (CaDR), explores a multi-level strategy of utilizing DDC for refining intrinsic evolution of analog computational circuits to construct building blocks, known as Constituent Functional Blocks (CFBs). The CFBs are developed in a cascaded sequence followed by digital evolution of higher-level control of these CFBs to build the final solution for the larger circuit at-hand. One such platform, Cypress PSoC-5LP was utilized to realize solutions to ordinary differential equations by first evolving various powers of the independent variable followed by that of their combinations to emulate mathematical series-based solutions for the desired range of values. This is shown to enhance accuracy and precision while incurring lower computational energy and time overheads. The fitness function for each CFB being evolved is different from the fitness function that is defined for the overall problem.

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Nowadays pervasive computing opens up many new challenges. Personal and sensitive data and computations are distributed over a wide range of computing devices. This presents great challenges in cryptographic system designs: how to protect privacy, authentication, and integrity in this distributed and connected computing world, and how to satisfy the requirements of different platforms, ranging from resource constrained embedded devices to high-end servers. Moreover, once mathematically strong cryptographic algorithms are implemented in either software or hardware, they are known to be vulnerable to various implementation attacks. Although many countermeasures have been proposed, selecting and integrating a set of countermeasures thwarting multiple attacks into a single design is far from trivial. Security, performance and cost need to be considered together. The research presented in this dissertation deals with the secure and efficient implementation of cryptographic primitives. We focus on how to integrate cryptographic coprocessors in an efficient and secure way. The outcome of this research leads to four contributions to hardware security research. First, we propose a programmable and parallel Elliptic Curve Cryptography (ECC) coprocessor architecture. We use a systematic way of analyzing the impact of System-on-Chip (SoC) integration to the cryptographic coprocessor performance and optimize the hardware/software codesign of cryptographic coprocessors. Second, we provide a hardware evaluation methodology to the NIST SHA-3 standardization process. Our research efforts cover both of the SHA-3 fourteen Second Round candidates and five Third Round finalists. We design the first SHA-3 benchmark chip and discuss the technology impact to the SHA-3 hardware evaluation process. Third, we discuss two technology dependent issues in the fair comparison of cryptographic hardware. We provide a systematic approach to do a cross-platform comparison between SHA-3 FPGA and ASIC benchmarking results and propose a methodology for lightweight hash designs. Finally, we provide guidelines to select implementation attack countermeasures in ECC cryptosystem designs. We discuss how to integrate a set of countermeasures to resist a collection of side-channel analysis (SCA) attacks and fault attacks. The first part of the dissertation discusses how system integration can affect the efficiency of the cryptographic primitives. We focus on the SoC integration of cryptographic coprocessors and analyze the system profile in a co-simulation environment and then on an actual FPGA-based SoC platform. We use this system-level design flow to analyze the SoC integration issues of two block ciphers: the existing Advanced Encryption Standard (AES) and a newly proposed lightweight cipher PRESENT. Next, we use hardware/software codesign techniques to design a programmable ECC coprocessor architecture which is highly flexible and scalable for system integration into a SoC architecture. The second part of the dissertation describes our efforts in designing a hardware evaluation methodology applied to the NIST SHA-3 standardization process. Our Application Specific Integrated Circuit (ASIC) implementation results of five SHA-3 finalists are the first ASIC real measurement results reported in the literature. As a contribution to the NIST SHA-3 competition, we provide timely ASIC implementation cost and performance results of the five SHA-3 finalists in the SHA-3 standard final round evaluation process. We define a consistent and comprehensive hardware evaluation methodology to the NIST SHA-3 standardization process from Field Programmable Gate Array (FPGA) prototyping to ASIC implementation. The third part of the dissertation extends the discussion on hardware benchmarking of NIST SHA-3 candidates by analyzing the impact of technology to the fair comparison of cryptographic hardware. First, a cross-platform comparison between the FPGA and ASIC results of SHA-3 designs demonstrates the gap between two sets of benchmarking results. We describe a systematic approach to analyze a SHA-3 hardware benchmark process for both FPGAs and ASICs. Next, by observing the interaction of hash algorithm design, architecture design, and technology mapping, we propose a methodology for lightweight hash implementation and apply it to CubeHash optimizations. Our ultra-lightweight design of the CubeHash algorithm represents the smallest ASIC implementation of this algorithm reported in the literature. Then, we introduced a cost model for analyzing the hardware cost of lightweight hash implementations. The fourth part of the dissertation discusses SCA attacks and fault attacks resistant cryptosystem designs. We complete a comprehensive survey of state-of-the-art of secure ECC implementations and propose a methodology on selecting countermeasures to thwart multiple side-channel attacks and fault attacks. We focus on a systematic way of organizing and understanding known attacks and countermeasures. / Ph. D.

Industrial Control Systems (ICSs) manage critical infrastructures such as water treatment facilities, petroleum refineries, and power plants. ICSs are networked through Information Technology (IT) infrastructure for remote monitoring and control of physical processes. As ICSs integrate with IT infrastructure, IT vulnerabilities are carried over to the ICS environment. Previously proposed process controller security architectures maintain safe and stable plant operation even in the presence of attacks that exploit ICS vulnerabilities. Security architectures are process control system-level solutions that leverage isolated and trusted hardware (secure enclaves) for ICS security. Upon detecting an intrusion, the secure enclave switches control of the physical process to a high assurance controller, making a fail-safe plant operation. The process control loop components have an average lifespan of several decades. During this time, electromechanical components of process control loop may undergo aging that alters their characteristics and affects control loop performance. To deal with component aging and to improve control algorithm flexibility, updates to control loop parameters are required. Plant model, process control loop system specifications, and control algorithm-based security mechanisms at the secure enclave require parameter updates. ICSs have hundreds of process control components that may need be installed in hazardous environments and distributed across hundreds of square kilometers. Updating each component physically may lead to accidents, expensive travel, and increased downtime. Some ICS have allowable downtime of only 5 minutes per year. Hence, remote updates are desirable. A proposed dedicated and isolated hardware module at the secure enclave provides authentication of the update and ensures safe storage in a non-volatile memory. A protocol designed for update transmission through an untrusted ICS network provides resilience against network integrity attacks such as replay attacks. Encryption and authentication of the updates maintain integrity and confidentiality. During the normal plant operation, the hardware module is invisible to the other modules of the process control loop. The proposed solution is implemented on Xilinx Zynq-7000 programmable System-on-Chip to provide secure enclave updates. / Master of Science