Les circuits microélectroniques récents intègrent des dizaines d'horloges afin d'optimiser leur consommation et leur performance. Le nombre de traversées de domaines d'horloges (CDC) et la complexité des systèmes augmentant, garantir formellement l'intégrité d'une donnée devient un défi majeur. Plusieurs problèmes sont alors soulevés : configurer le système dans un mode réaliste, décrire l'environnement par des hypothèses sur les protocoles, gérer l'explosion de l'espace des états, analyser les contre-exemples, ...La première contribution de cette thèse a pour but d'atteindre une configuration complète et réaliste du système. Nous utilisons de la vérification formelle paramétrique ainsi qu'une analyse de la structure du circuit afin de détecter automatiquement les composants des arbres d'horloge. La seconde contribution cherche à éviter l'explosion de l'espace des états en combinant des abstractions localisées du circuit avec une analyse de contre-examples. L'idée clé est d'utiliser la technologie de raffinement d'abstraction guidée par contre-exemple (CEGAR) où l'utilisateur influence la poursuite de l'algorithme en se basant sur des informations extraites des contre-exemples intermédiaires. La troisième contribution vise à créer des hypothèses pour des environnements sous-contraints. Tout d’abord, plusieurs contre-exemples sont générés pour une assertion, avec différentes raisons d’échec. Ensuite, des informations en sont extraites et transformées en hypothèses réalistes.Au final, cette thèse montre qu'une vérification formelle concluante peut être obtenue en combinant la rapidité de l'analyse structurelle avec l'exhaustivité des méthodes formelles. / Modern hardware designs typically comprise tens of clocks to optimize consumption and performance to the ongoing tasks. With the increasing number of clock-domain crossings as well as the huge complexity of modern SoCs, formally proving the functional integrity of data propagation became a major challenge. Several issues arise: setting up the design in a realistic mode, writing protocol assumptions modeling the environment, facing state-space explosion, analyzing counter-examples, ...The first contribution of this thesis aims at reaching a complete and realistic design setup. We use parametric liveness verification and a structural analysis of the design in order to identify behaviors of the clock and reset trees. The second contribution aims at avoiding state-space explosion, by combining localization abstractions of the design, and counter-example analysis. The key idea is to use counterexample-guided abstraction refinement as the algorithmic back-end, where the user influence the course of the algorithm based on relevant information extracted from intermediate abstract counterexamples. The third contribution aims at creating protocol assumptions for under-specified environments. First, multiple counter-examples are generated for an assertion, with different causes of failure. Then, information is mined from them and transformed into realistic protocol assumptions.Overall, this thesis shows that a conclusive formal verification can be obtained by combining inexpensive structural analysis along with exhaustive model checking.

Este trabalho aborda um sistema de aquisição de dados (SAD) analógico-digital, baseado em um esquema redundante com diversidade de projeto, que é testado em dois ambientes diferentes de radiação. O primeiro experimento considera um teste de dose total ionizante (Total Ioninzig Dose - TID) sob irradiação gama, e o segundo experimento considera os efeitos de eventos singulares (Single Event Effects - SEE) sob irradiação por íons pesados. O SAD é composto, principalmente, por três conversores analógicos-digitais (ADCs) e dois votadores. A técnica usada é a Redundância Modular Tripla (Triple Modular Redundancy - TMR), com implementação em diferentes níveis de diversidade (temporal e arquitetural). O sistema é construído em um System-on-Chip programável (PSoC 5LP) da Cypress Semiconductor, fabricado em tecnologia CMOS de 130nm. Para a irradiação com TID, se utiliza o PSoC de part number CY8CKIT-050 sob uma fonte de radiação gama de 60Co (cobalto-60), com uma taxa de dose efetiva de 1 krad(Si)/h por 10 dias, atingindo uma dose total de 242 krad(Si) Para SEE se utiliza o protótipo PSoC de part number CY8CKIT-059 (sem encapsulamento) em um acelerador de partículas 8UD Pelletron usando 16O (oxigeno-16) ao vácuo, com energia de 36 MeV em um LET aproximado de 5.5 MeV/mg/cm2 e uma penetração no silício de 25 mm, resultando em um fluxo de 354 p/cm2.s, e uma fluência de 5077915 p/cm2 depois de 14755 segundos (4h 09min). Observou-se com o resultado do primeiro estudo que um (1) dos módulos do sistema apresentou uma degradação significativa na sua linearidade durante a irradiação, enquanto os outros tiveram uma degradação menos grave, mantendo assim a funcionalidade e confiabilidade do sistema. Durante o tempo de irradiação do segundo estudo, foram observadas 139 falhas: 53 SEFIs (Single Events Funtional Interrupt), 29 falhas críticas e 57 falhas SDC (Silent Data Corruption), atingindo as diferentes copias do sistema e um dos votadores do mesmo, mas sempre mantendo a saída esperada. Nos dois experimentos se evidencia a vantagem de usar a diversidade de projeto, além do TMR, para melhorar a resiliência e confiabilidade em sistemas críticos redundantes que trabalham com sinais mistos. / This work presents an analog-to-digital data acquisition system (DAS) based on a redundant scheme with design diversity, being tested in two different radiation environments. The first experiment is a Total Ionizing Dose (TID) essay and the second one considers Single Event Effects (SEE) under heavy ion irradiation. The DAS is mainly composed of three analog-todigital converters (ADCs) and two voters. The used technique was the Triple Modular Redundancy (TMR) implementing different levels of diversity (temporal and architectural). The circuit was built in a programmable System-on-Chip (PSoC 5LP) from Cypress Semiconductor, fabricated in a 130nm CMOS technology process. For the irradiation with TID the part number CY8CKIT-050 PSoC was used under a 60Co (cobalt-60) gamma radiation source, with an effective dose rate of 1 krad(Si)/h during 10 days, reaching a total dose of 242 krad(Si). For SEE experiments the part number CY8CKIT-059 (without encapsulation) PSoC prototype under a 8UD Pelletron particle accelerator using 16O (oxigen-16) under vacuum, with an energy of 36 MeV, resulting in a flux of 354p/cm2.s and a fluence of 5077915p/cm2 after 14755 seconds (4h 09min). As result of the first study it was observed that one of the system’s modules presented a significant degradation in its linearity during the irradiation, while degradations in the other modules were not as deep, maintaining the system’s functionality and reliability. During the period of the radiation of the second study, 139 faults were observed, 82 of them were critical and 57 were SDC (Silent Data Corruption), reaching the different system copies and one of the voters, while always maintaining the correct output. The advantage of using diversity, besides TMR, to improve resilience and reliability in redundant systems working with mixed signals was demonstrated in both experiments.

Ce travail s'inscrit dans le contexte du retraitement du combustible irradié dans l'industrie nucléaire. La gestion du combustible usé fait partie des enjeux majeurs de l'industrie nucléaire aujourd'hui. Ses vastes implications sont de nature économique, politique et écologique. Puisque le combustible irradié contient 97 % des matières valorisables, de nombreux pays ont choisi de retraiter le combustible, non tant pour des raisons économiques que pour le besoin de réduire la quantité en déchets radiotoxiques. Le procédé de séparation le plus répandu est connu sous le nom PUREX et consiste à diluer le combustible dans une solution d'acide nitrique afn d'en extraire les matières valorisables, comme notamment l'uranium et le plutonium. Le procédé est soumis à des strictes contrôles qui s'effectuent au présent par prélèvement et analyse manuel des flux radiotoxiques. Il n'existe cependant peu d'outils pour la supervision du procédé en ligne. Ces travaux visent alors à développer un capteur adapté à cet environnement de mesure à la fois acide et ionisant. Les verres borosilicates étant répandus pour leur inertie chimique, nous proposons l'étude d'un capteur optique fondé sur le substrat de verre Borofloat 33 de Schott. Le capteur étudié et réalisé a été fabriqué grâce à deux technologies différentes : l'optique intégrée sur verre par échange d'ions pour la fabrication de fonction de guidage optique, et la microfluidique pour la gestion des flux acides au sein du capteur. L'approche optique permet de répondre aux besoins de polyvalence, de sensibilité et d'immunité au rayonnement électromagnétique. La microfluidique permet, quant à elle, de travailler sur des très faibles volumes d'échantillon, réduisant ainsi la radiotoxicité des flux d'analyse. Le principe de mesure du capteur repose sur l'effet photothermique, induit dans le fluide par absorption optique d'un faisceau laser d'excitation. L'absorption entraîne un changement de l'indice de réfraction du fluide qui est sondé par un interféromètre de Young, intégré sur la puce. Le volume sondé au sein du canal était de (33,5 ± 3,5) pl. Le changement d'indice de réfraction à la limite de détection était de ∆n_min = 1,2 × 10−6 , nous permettant de détecter une concentration minimale de cobalt(II) dans de l'éthanol de c_min = 6 × 10−4 mol/l, équivalent à un coefficient d'absorption de alpha_min = 1,2 × 10−2 cm−1. À la limite de détection du capteur, une quantité de N_min = (20 ± 2) fmol de cobalt(II) peut être détectée. La longueur d'interaction était de li = 14,9 µm et par conséquent l'absorbance minimale détectable égal K_min = (1,56±0,12)×10−5. / This work has been done in the context of fuel reprocessing in the nuclear industry. In fact, the handling of nuclear waste is one of the major issues in the nuclear industry. Its implications reach from economical to political to ecological dimensions. Since used nuclear fuel consists of 97 % of recyclable substances, many countries have chosen to reprocess used fuel, not only for economical reasons but also to limit the quantity of nuclear waste. The most widely employed extraction technique is the PUREX process, where the used fuel is diluted in nitric acid. The recyclable compounds can then be extracted by solvent techniques. Such processes need to be monitored crucially. However, nowadays, the process supervision is carried out by manually sampling the radioactive fluents and analyzing them in external laboratories. Not only prone to potential risks, this approach is little responsive and produces radiotoxic samples that cannot be reintroduced in the nuclear fuel cycle. In this study, we therefore present the development of a microfluidic glass sensor, based on the detection of a photothermal effect induced in the sample fluid. Microfluidics allows fluid handling on a microliter-scale and can therefore significantly reduce the sample volume and thereby the radiotoxcicity of the analyzed fluids. Photothermal spectrometry is well suited for small-scale sample analysis, since its sensitivity does not rely on the length of optical interaction with the analyte. The photothermal effect is a local refractive index variation due to the absorption of photons by the analyte species which are contained in the sample. On the sensor chip, the index refraction change is being sensed by an integrated Young interferometer, made by ion-exchange in glass. The probed volume in the channel was (33.5 ± 3.5) pl. The interferometric system can sense refractive index changes as low as ∆n_min = 1.2 × 10−6 , allowing to detect a minimum concentration of cobalt(II) in ethanol c_min = 6 × 10−4 mol/l, which is equivalent to an absorption coefficient of alpha_min = 1.2 × 10−2 cm−1 . At the detection limit, we could sense an absolute quantity of cobalt(II) of N_min = (20 ± 2) fmol. The interaction length between the excitation light and the sensing zone was li = 14.9 µm leading to a minimum detectable absorbance of K_min = (1.56 ± 0.12) × 10−5 .

L'utilisation de la troisième dimension peut entraîner une réduction significative de la puissance et de la latence moyenne du trafic dans les réseaux sur puce (Network-on-Chip). La technologie des vias à travers le substrat (ou Through-Silicon Via) est la technologie la plus prometteuse pour l'intégration 3D, car elle offre des liens verticaux courts qui remédient au problème des longs fils dans les NoCs-2D. Les TSVs sont cependant énormes et les processus de fabrication sont immatures, ce qui réduit le rendement des systèmes sur puce à base de NoC-3D. Par conséquent, l'idée de réseaux sur puce 3D partiellement connectés verticalement a été introduite pour bénéficier de la technologie 3D tout en conservant un haut rendement. En outre, de tels réseaux sont flexibles, car le nombre, l'emplacement et l'affectation des liens verticaux dans chaque couche peuvent être décidés en fonction des exigences de l'application. Cependant, ce type de réseaux pose un certain nombre de défis : Le routage est le problème majeur, car l'élimination de certains liens verticaux fait que l'on ne peut utiliser les algorithmes classiques qui suivent l'ordre des dimensions. Pour répondre à cette question nous expliquons et évaluons un algorithme de routage déterministe appelé “Elevator First”, qui garanti d'une part que si un chemin existe, alors on le trouve, et que d'autre part il n'y aura pas d'interblocages. Fondamentalement, la performance du NoC est affecté par a) la micro architecture des routeurs et b) l'architecture d'interconnexion. L'architecture du routeur a un effet significatif sur la performance du NoC, à cause de la latence qu'il induit. Nous présentons la conception et la mise en œuvre de la micro-architecture d'un routeur à faible latence implantant​​l'algorithme de routage Elevator First, qui consomme une quantité raisonnable de surface et de puissance. Du point de vue de l'architecture, le nombre et le placement des liens verticaux ont un rôle important dans la performance des réseaux 3D partiellement connectés verticalement, car ils affectent le nombre moyen de sauts et le taux d'utilisation des FIFOs dans le réseau. En outre, l'affectation des liens verticaux vers les routeurs qui n'ont pas de ports vers le haut ou/et le bas est une question importante qui influe fortement sur les performances. Par conséquent, l'exploration architecturale des réseaux sur puce 3D partiellement connectés verticalement est importante. Nous définissons, étudions et évaluons des paramètres qui décrivent le comportement du réseau, de manière à déterminer le placement et l'affectation des liens verticaux dans les couches de manière simple et efficace. Nous proposons une méthode d'estimation quadratique visantà anticiper le seuil de saturation basée sur ces paramètres. / Utilization of the third dimension can lead to a significant reduction in power and average hop-count in Networks- on-Chip (NoC). TSV technology, as the most promising technology in 3D integration, offers short and fast vertical links which copes with the long wire problem in 2D NoCs. Nonetheless, TSVs are huge and their manufacturing process is still immature, which reduces the yield of 3D NoC based SoC. Therefore, Vertically-Partially-Connected 3D-NoC has been introduced to benefit from both 3D technology and high yield. Moreover, Vertically-Partially-Connected 3D-NoC is flexible, due to the fact that the number, placement, and assignment of the vertical links in each layer can be decided based on the limitations and requirements of the design. However, there are challenges to present a feasible and high-performance Vertically-Partially-Connected Mesh-based 3D-NoC due to the removed vertical links between the layers. This thesis addresses the challenges of Vertically-Partially-Connected Mesh-based 3D-NoC: Routing is the major problem of the Vertically-Partially-Connected 3D-NoC. Since some vertical links are removed, some of the routers do not have up or/and down ports. Therefore, there should be a path to send a packet to upper or lower layer which obviously has to be determined by a routing algorithm. The suggested paths should not cause deadlock through the network. To cope with this problem we explain and evaluate a deadlock- and livelock-free routing algorithm called Elevator First. Fundamentally, the NoC performance is affected by both 1) micro-architecture of routers and 2) architecture of interconnection. The router architecture has a significant effect on the performance of NoC, as it is a part of transportation delay. Therefore, the simplicity and efficiency of the design of NoC router micro architecture are the critical issues, especially in Vertically-Partially-Connected 3D-NoC which has already suffered from high average latency due to some removed vertical links. Therefore, we present the design and implementation the micro-architecture of a router which not only exactly and quickly transfers the packets based on the Elevator First routing algorithm, but it also consumes a reasonable amount of area and power. From the architecture point of view, the number and placement of vertical links have a key role in the performance of the Vertically-Partially-Connected Mesh-based 3D-NoC, since they affect the average hop-count and link and buffer utilization in the network. Furthermore, the assignment of the vertical links to the routers which do not have up or/and down port(s) is an important issue which influences the performance of the 3D routers. Therefore, the architectural exploration of Vertically-Partially-Connected Mesh-based 3D-NoC is both important and non-trivial. We define, study, and evaluate the parameters which describe the behavior of the network. The parameters can be helpful to place and assign the vertical links in the layers effectively. Finally, we propose a quadratic-based estimation method to anticipate the saturation threshold of the network's average latency.

Este trabalho aborda um sistema de aquisição de dados (SAD) analógico-digital, baseado em um esquema redundante com diversidade de projeto, que é testado em dois ambientes diferentes de radiação. O primeiro experimento considera um teste de dose total ionizante (Total Ioninzig Dose - TID) sob irradiação gama, e o segundo experimento considera os efeitos de eventos singulares (Single Event Effects - SEE) sob irradiação por íons pesados. O SAD é composto, principalmente, por três conversores analógicos-digitais (ADCs) e dois votadores. A técnica usada é a Redundância Modular Tripla (Triple Modular Redundancy - TMR), com implementação em diferentes níveis de diversidade (temporal e arquitetural). O sistema é construído em um System-on-Chip programável (PSoC 5LP) da Cypress Semiconductor, fabricado em tecnologia CMOS de 130nm. Para a irradiação com TID, se utiliza o PSoC de part number CY8CKIT-050 sob uma fonte de radiação gama de 60Co (cobalto-60), com uma taxa de dose efetiva de 1 krad(Si)/h por 10 dias, atingindo uma dose total de 242 krad(Si) Para SEE se utiliza o protótipo PSoC de part number CY8CKIT-059 (sem encapsulamento) em um acelerador de partículas 8UD Pelletron usando 16O (oxigeno-16) ao vácuo, com energia de 36 MeV em um LET aproximado de 5.5 MeV/mg/cm2 e uma penetração no silício de 25 mm, resultando em um fluxo de 354 p/cm2.s, e uma fluência de 5077915 p/cm2 depois de 14755 segundos (4h 09min). Observou-se com o resultado do primeiro estudo que um (1) dos módulos do sistema apresentou uma degradação significativa na sua linearidade durante a irradiação, enquanto os outros tiveram uma degradação menos grave, mantendo assim a funcionalidade e confiabilidade do sistema. Durante o tempo de irradiação do segundo estudo, foram observadas 139 falhas: 53 SEFIs (Single Events Funtional Interrupt), 29 falhas críticas e 57 falhas SDC (Silent Data Corruption), atingindo as diferentes copias do sistema e um dos votadores do mesmo, mas sempre mantendo a saída esperada. Nos dois experimentos se evidencia a vantagem de usar a diversidade de projeto, além do TMR, para melhorar a resiliência e confiabilidade em sistemas críticos redundantes que trabalham com sinais mistos. / This work presents an analog-to-digital data acquisition system (DAS) based on a redundant scheme with design diversity, being tested in two different radiation environments. The first experiment is a Total Ionizing Dose (TID) essay and the second one considers Single Event Effects (SEE) under heavy ion irradiation. The DAS is mainly composed of three analog-todigital converters (ADCs) and two voters. The used technique was the Triple Modular Redundancy (TMR) implementing different levels of diversity (temporal and architectural). The circuit was built in a programmable System-on-Chip (PSoC 5LP) from Cypress Semiconductor, fabricated in a 130nm CMOS technology process. For the irradiation with TID the part number CY8CKIT-050 PSoC was used under a 60Co (cobalt-60) gamma radiation source, with an effective dose rate of 1 krad(Si)/h during 10 days, reaching a total dose of 242 krad(Si). For SEE experiments the part number CY8CKIT-059 (without encapsulation) PSoC prototype under a 8UD Pelletron particle accelerator using 16O (oxigen-16) under vacuum, with an energy of 36 MeV, resulting in a flux of 354p/cm2.s and a fluence of 5077915p/cm2 after 14755 seconds (4h 09min). As result of the first study it was observed that one of the system’s modules presented a significant degradation in its linearity during the irradiation, while degradations in the other modules were not as deep, maintaining the system’s functionality and reliability. During the period of the radiation of the second study, 139 faults were observed, 82 of them were critical and 57 were SDC (Silent Data Corruption), reaching the different system copies and one of the voters, while always maintaining the correct output. The advantage of using diversity, besides TMR, to improve resilience and reliability in redundant systems working with mixed signals was demonstrated in both experiments.

The technology today makes it possible to integrate a complete system on a single chip, called "System-on-Chip'' (SOC). Nowadays SOC designers use previously designed hardware modules, called cores, together with their user defined logic (UDL), to form a complete system on a single chip. The manufacturing process may result in defect chips, for instance due to the base material, and therefore testing chips after production is important in order to ensure fault-free chips. The testing time for a chip will affect its final cost. Thus it is important to minimize the testing time for each chip. For core-based SOCs this can be done by testing several cores at the same time, instead of testing the cores sequentially. However, this will result in a higher activity in the chip, hence higher power consumption. Due to several factors in the manufacturing process there are limitations of the power consumption for a chip. Therefore, the power limitations should be carefully considered when planning the testing of a chip. Otherwise it can be damaged during test, due to overheating. This leads to the problem of minimizing testing time under such power constraints. In this thesis we discuss test power modeling and its application to SOC testing. We present previous work in this area and conclude that current power modeling techniques in SOC testing are rather pessimistic. We therefore propose a more accurate power model that is based on the analysis of the test data. Furthermore, we present techniques for test pattern reordering, with the objective of partitioning the test power consumption into low parts and high parts. The power model is included in a tool for SOC test architecture design and test scheduling, where the scheduling heuristic is designed for SOCs with fixed- width test bus architectures. Several experiments have been conducted in order to evaluate the proposed approaches. The results show that, by using the presented power modeling techniques in test scheduling algorithms, we will get lower testing times and thus lower test cost.

A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific System on Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for Chip Multi Processor (CMP) case that can solve the ASSoC scenario also.

Orientador: Aílton Akira Shinoda / Resumo: Bastidores eletrônicos de alta performance e disponibilidade utilizam o protocolo Intelligent Platform Management Interface (IPMI) para gerenciar seus dispositivos, controlando e monitorando os recursos disponíveis. Neste contexto para inserir dispositivos com tecnologia mais avançada, novos projetos foram elaborados para atualização dos sistemas de hardware e software baseados em System-on-Chip (SoC), principalmente na área de Física de Alta Energia. Uma aplicação existente, desenvolvida na parceira São Paulo Research and Analysis Center – Fermi National Accelerator Laboratory (SPRACE–FERMILAB) na colaboração internacional do Compact Muon Solenoid detector/Large Hadron Collider/European Organization for Nuclear Research (CMS/LHC/CERN), utiliza o protocolo IPMI implementado em um microcontrolador, contudo, para o processo de atualização vigente, há um interesse desta implementação em SoC. Assim, esta pesquisa foi desenvolvida como o estudo da viabilidade da implementação IPMI em um SoC. Para estabelecer e verificar o protocolo IPMI via barramento I²C, a plataforma Xilinx ZC702 Evaluation Board foi utilizada com os respectivos dispositivos SoC Zynq e Erasable Programmable Memory (EEPROM). Além disso foi desenvolvido uma estrutura simples do IPMI no sistema operacional em tempo real (FreeRTOS) baseados em modelos de hardware e software criados na plataforma Xilinx IDE e SDK. Por meio dos resultados apresentados é possível constatar a viabilidade da implementação IPMI em sistema... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: High performance and availability electronic racks use the Intelligent Platform Management Interface (IPMI) protocol to manage your devices by controlling and monitoring available resources. In this context to insert devices with more advanced technology, new projects were elaborated to update the System-on-Chip (SoC) based hardware and software systems, mainly in the area of High Energy Physics. An existing application developed at the São Paulo Research and Analysis Center partner - Fermi National Accelerator Laboratory (SPRACE – FERMILAB) in the international collaboration of the Compact Muon Solenoid detector/Large Hadron Collider/European Organization for Nuclear Research (CMS/LHC/CERN) uses The IPMI protocol implemented in a microcontroller, however, for the current update process, there is an interest of this implementation in SoC. Thus, this research was developed as the study of the viability of implementing IPMI in a SoC. To establish and verify the IPMI protocol via I²C bus, the Xilinx ZC702 Evaluation Board platform was used with the respective SoC Zynq and Erasable Programmable Memory (EEPROM) devices. In addition, a simple IPMI framework in the real time operating system (FreeRTOS) based on hardware and software models created on the Xilinx IDE and SDK platform was developed. From the results presented, it is possible to verify the viability of IPMI implementation in systems such as SoC Zynq as platform management controller, which allows migration and further t... (Complete abstract click electronic access below) / Mestre

Les appareils multimédias portables nécessitent toujours plus d'innovation pour satisfaire les besoins des utilisateurs. Les fabricants de système-sur-puces font donc face à une forte demande en capacité de calcul jusqu'à lors réservée aux ordinateurs de bureau. Ce transfert de performance se répercute inévitablement sur la consommation de ces appareils alors que dans le même temps la capacité des batteries n'est pas en mesure de répondre à cet accroissement. De nombreux compléments matériels et logiciels sont mis en places afin d'économiser l'énergie au maximum sans toutefois dégrader les performances. La modulation de la fréquence de fonctionnement et de la tension d'alimentation est certainement la plus efficace mais reste néanmoins limitée par les coûts et les contraintes d'encombrement exigées par la taille des appareils. La réponse à un tel problème passe nécessairement par l'intégration d'une partie de l'alimentation dans la puce. La conversion DC-DC basée sur des convertisseurs à capacités commutées est prometteuse car elle permet de garder un maximum de compatibilité avec les process CMOS actuels. Cette thèse explore donc la conception d'une architecture d'alimentation utilisant des convertisseurs à capacités commutées. Un étage de puissance avec une tension d'entrée est de 1.8 V et des ratios programmables permet d'obtenir le rendement maximum pour une plage de tension de sortie allant de 0.3 à 1.2 V. La tension de sortie peut varier en fonction du point de fonctionnement requit par le système. Afin d'assurer le maximum de compatibilité avec la conception du circuit numérique à alimenter, une architecture modulaire basée sur les capacités MIM est privilégiée. Les capacités sont placées au dessus de la fonction numériques et les interrupteurs de puissance sont insérés à sa périphérie. Cette architecture permet également d'entrelacer les cellules de conversion afin de réduire l'ondulation de la tension de sortie. La fréquence de commutation du convertisseurs est communément utilisée pour réguler la tension de sortie et des stratégies de contrôles linéaires et non linéaires sont donc explorées. Un prototype de convertisseur présentant une densité de puissance de 310mW/mm2 pour un rendement de 72.5% a été fabriqué dans la technologie 28nm FDSOI de STMicroelectronics. La surface requise pour le convertisseur nécessite que 11.5% de la surface du circuit à alimenter. La méthodologie de conception du convertisseur a finalement été appliquée à un régulateur de tension dans le domaine négatif pour des applications de polarisation de caisson à basse consommation. / Mobile and multimedia devices offer more innovations and enhancements to satisfy user requirements. Chip manufacturers thus propose high performances SoC to address these needs. Unfortunately the growth in digital resources inevitably increases the power consumption while battery life-time does not rise as fast. Aggressive power management techniques such as dynamic voltage and frequency scaling have been introduced in order to keep competitive and relevant solutions. Nonetheless continuing in this direction involves more disruptive solutions to meet space and cost constraints. Fully integrated power supply is a promising solution. Switched-capacitor DC-DC converters seem to be a suitable candidate to keep compatibility with the manufacturing process of digital SoCs. This thesis focuses on the design of an embedded power supply architecture using switched-capacitor DC-DC converters.Addressing a large range of output power with significant efficiency leads to consider a multi-ratio power stage. With respect to the typical digital SoC, the input voltage is 1.8 V and the converter is specified to deliver an output voltage in the 0.3-1.2 V range. The reference voltage is varying according to typical DVFS requirements. A modular architecture accommodates the digital design flow where the flying capacitors are situated above the digital block to supply and the power switches are located as an external ring. Such an architecture offers high flexibility. Interleaving strategy is considered to mitigate the output voltage ripple. Such a converter admits the switching frequency as a control variable and linear regulation and hysteretic control are analyzed. A prototype has been fabricated in 28nm FDSOI technology by STMicroelectronics. A power density of 310 mW/mm2 is achieved at 72.5% peak efficiency with a silicon area penalty of 11.5% of the digital block area. The successful design methodology has been also applied to the design of a negative SC converter for body-biasing purpose in FDSOI. Simulation results demonstrate a strong interest for low power application.

In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two chips, one FPGA and a processor, to an internal bus implemented on only one chip, System on Chip. The work is based on measurements made in real time in Xilinx’s development tools on different buses, AXI4 and AXI4-Light connected to AXI3. The port that is used is FPGA’s own GP-port. Besides measuring the time of transactions also physical aspects have been investigated in this project: space, costs and time. Based on those criteria a comparison to the original construction was made to determine which benefits that can be achieved. The work has shown a number of results that are in comparison with the original construction. The System on Chip has turned out to be a better solution in most cases. When using the AXI4-Light-bus the benefits were not as obvious. Cosmic radiation, temperature or humidity are beyond the scope of this investigation. In the work the hypothetic deductive method has been used to prove that the System on Chip is faster than the original design. In this method three statements must be set up against each other; one statement that ought to be true, one statement that is a contradiction and a conclusion of what is proved. The pre-study pointed out that the System on Chip is a faster solution than the original construction. The method is useful since it proves that the pre-study is comparable to the measured results. / I detta examensarbete har undersökningar gjorts för att fastställa vilka vinster som går att göra genom att byta en internbuss mellan två chip, en FPGA och en processor, mot en intern buss implementerat på ett enda chip, System on Chip. Arbetet bygger på mätningar gjorda i realtid i Xilinx utvecklingsverktyg på olika bussar, AXI4 och AXI4‑Lite som är kopplade internt mot AXI3. Den port som används är FPGAs egen GP‑port. Förutom att mäta överföringshastigheterna, har även fysiska aspekter som utrymme, kostnader och utvecklingstid undersökts. Utifrån dessa kriterier har en jämförelse gjorts med den befintliga konstruktionen för att fastställa vilka vinster som går att uppnå. Arbetet har resulterat i ett antal resultat som är ställda mot de förutsättningar som fanns i den ursprungliga lösningen. I de flesta fall visar resultatet att ett System on Chip är en bättre lösning. De fall som var tveksamma var vid viss typ av överföring med AXI4‑Lite bussen. I arbetet har inte undersökning av kosmisk strålning, temperatur eller luftfuktighet betraktas. I arbetet med att försöka att bevisa att ett System on Chip är snabbare än den ursprungliga uppsättningen har utvecklingsmetoden hypotetisk deduktiv använts. Denna metod bygger på att man från början sätter upp ett påstående, som man förutsätter är sant, följt av en konjunktion, som inte får inträffa, för att slutligen dra en slutsats, som konstaterar fakta. Eftersom fakta som lästes in i början av arbetet pekade på att ett System on Chip var en snabbare och billigare lösning kändes metoden användbar. Under arbetets gång har det visat sig vara en bra metod som också ger ett resultat där sannolikheten för att det är en snabbare lösning ökar. Däremot säger inte metoden att det är helt säkert att den i alla situationer är bättre, vilket kan ändras om man använder andra förutsättningar eller tar med andra aspekter.