Low-loss waveguides with minimal dispersion are desired throughout the electromagnetic spectrum. These properties are difficult to achieve in the Terahertz (THz) region due to material and geometric constraints. This thesis focuses on the design, fabrication, and testing of waveguide-based devices using two promising technologies: the free-space metallic-slit waveguide (MSWG) and the coplanar strip (CPS) waveguide on a thin (1 um) commercial silicon nitride membrane. The work presented here differs from standard THz waveguide research which commonly uses the field radiated by a photoconductive antenna (THz optics) for excitation and detection. To improve upon system integration, a focus is placed on planar waveguide devices without refractive THz elements. Three main waveguide devices are investigated. First, an edge-coupled MSWG-based linear tapered slot antenna (LTSA) was used for THz-Time Domain Spectroscopy (TDS). This device functions as an alternative to a standard photoconductive switch coupled to a silicon lens and maintains comparable performance. Next an edge-coupled tapered MSWG was investigated. The MSWG conductor separation was increased to a low-loss configuration where the field propagated for 24 mm, after which the conductors were tapered to focus the field onto the receiving active region where a THz-bandwidth pulse was detected. Finally a CPS waveguide was fabricated on a thin silicon nitride membrane where a THz-bandwidth pulse was detected after propagating for 10 mm. The active regions for this device were fabricated using a unique method. This method results in the creation of thousands of small (40 um x 20 um) active regions (from a 4 mm x 4 mm host substrate) which can be placed anywhere for THz excitation and detection. The small active regions in conjunction with the CPS waveguide on the silicon nitride membrane provide an excellent platform for THz system testing. A single membrane can host many THz circuits which can be made ``active" by the placement of a few thin-film photoconductive devices. Main potential future applications include waveguide-based spectroscopy and coherent THz-bandwidth circuit analysis. / Graduate

A complexidade crescente (tanto da funcionalidade como da arquitetura) dos sistemas eletrônicos digitais sobre silício (conhecidos na literatura como System-on-Chip, SoC) exige novas metodologias que permitam diminuir seu tempo de desenvolvimento. O projeto no nível de sistemas (SLD) é proposto para aumentar a eficiência do projeto de SoC. SLD exige novas linguagens (como SystemC) e níveis de abstração (como TLM). A estrutura de comunicação (EC) de um SoC tem apresentado uma crescente importância devido à presença de uma maior quantidade (e funcionalidade) dos módulos a serem comunicados. Portanto, a EC apresenta um grande impacto no desempenho global do SoC. Nesta tese é proposta uma metodologia de projeto da EC chamada de MaLOC (Multi- Abstraction Level On-Chip communications structure design) que é baseada num enfoque top-down que percorre três níveis de transações (TLM). A tomada de decisões é feita utilizando-se duas importantes características que dão a originalidade a nossa proposta: 1) baseadas num conjunto de diversas métricas de desempenho que permite obter resultados mais confiáveis. 2) decisões ASAP (o mais rápido possível), antecipando a tomada de decisões utilizando níveis mais abstratos do que o RTL, permitindo diminuir o tempo de projeto da EC. Para validar a proposta uma série de análises de fidelidade foram realizadas, os resultados indicaram fidelidades maiores do que 96% e em cenários extremos maiores do que 72%. Adicionalmente os tempos de simulação no nível TLM atemporal foi até 2,6 vezes mais rápido do que o nível TLM de precisão de transferências, que foi até 1,6 vezes mais rápido do que o nível TLM de ciclos de relógio (menos abstrato). Estes resultados indicam a validade da metodologia para realizar a tomada de decisões, permitindo uma melhor exploração do espaço de projeto Os estudos de caso permitiram observar que além de configurar a EC procurando o melhor desempenho, MaLOC identificou soluções com menor consumo de energia, através do uso de um conjunto diverso de métricas, e configuração de parâmetros do sistema (tamanho da memória). Estas duas situações indicam o potencial que a metodologia apresenta para o projeto de diferentes tipos de EC, assim como de diferentes componentes de um SoC. / Modern and future System on Chip design requires several methodologies in order to handle their growing complexity (of both functional and architectural issues). System Level Design has emerged as a solution to handle the complex of nowadays and future SoC designs, increasing their efficiency and reducing the time to market. SLD requires new modeling languages (such as SystemC) and abstraction levels (such as Transaction Level Modeling - TLM). The integration of very different and composite IP cores into a SoC makes their physical and logical integration a very difficult task. Hence, the communication structure (CS) presents a significant impact on the SOC global performance. This thesis proposes a novel methodology named MaLOC (Multi-Abstraction Level On- Chip communications structure design) that uses a top-down approach. The parameters configuration is driven by two important considerations: 1) performance metrics based, this enables to obtain a most reliable solution; 2) an ASAP configuration schedule, this enables to reduce the CS design time through the use of higher abstraction levels. A fidelity test was performed. The results showed that in extreme conditions (such as burst size higher than time between transactions) the fidelity obtained was higher than 72%. In normal cases (burst size similar to the time between transactions) the fidelity was higher than 96%. The simulations execution times were compared among the three TLM levels and the results showed that TLM untimed simulations were 2.6 times faster than the TLM transfer accurate, also these were 1.6 times faster than the TLM cycle accurate. This means that TLM untimed simulations are 4 times faster than TLM Cycle accurate, enabling a enhanced space design exploration. The case studies performed showed that MaLOC can be useful to identify solutions that satisfy the performance required reducing the power consumption (reducing activities across the bus). Also, a system parameter was defined using the methodology (memory banks). These two situations indicate the MaLOC potential to design several CS types and SoC configuration parameters.

This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool. A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy consumption. Loops in applications are identified and accelerated by tightly coupling a coprocessor to an ASIP (Application Specific Instruction-set Processor). Latency hiding is used to exploit the parallelism provided by this architecture. A case study has been performed on a JPEG encoding algorithm; comparing two different coprocessor approaches: a high-level synthesis approach and our custom coprocessor approach. The thesis concludes by introducing a heterogenous multi-processor system using ASIPs as processing entities in a pipeline configuration. The problem of mapping each algorithmic stage in the system to an ASIP configuration is formulated. We proposed an estimation technique to calculate runtimes of the configured multiprocessor system without running cycle-accurate simulations, which could take a significant amount of time. We present two heuristics to efficiently search the design space of a pipeline-based multi ASIP system and compare the results against an exhaustive approach. In our first approach, we show that, on average, processor size can be reduced by 30%, energy consumption by 24%, while performance is improved by 24%. In the coprocessor approach, compared with the use of a main processor alone, a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, as against 1.58x for the high level synthesis method, and 1.33x for the customized instruction approach. Energy savings are 57%, 28% and 19%, respectively. Our multiprocessor design provides a performance improvement of at least 4.03x for JPEG and 3.31x for MP3, for a single processor design system. The minimum cost obtained using our heuristic was within 0.43% and 0.29% of the optimum values for the JPEG and MP3 benchmarks respectively.

Ce document retrace mes activités de recherche depuis ma thèse soutenue en juillet 1997. Certains des travaux présentés sont achevés, d'autres sont en cours ou encore dans un stade exploratoire. De 1993 à 1999, je me suis intéressé aux différents aspects du <br />partitionnement logiciel/matériel dans la conception de systèmes intégrés numériques de télécommunications. Depuis 1999, mes travaux ont porté sur la conception de systèmes multiprocesseurs monopuces, et plus particulièrement sur ce qui a trait aux relations entre <br />logiciel et matériel. Ces systèmes sont généralement dédiés à une application ou à une classe d'applications, ce qui permet d'optimiser l'architecture et les programmes. Mes recherches ses sont donc <br />focalisées sur l'architecture mémoire, les interfaces de <br />communication entre composants et le prototypage. Pour ces trois axes de recherche, des méthodes et des outils d'aide à la conception ont été définis et développés. Des travaux toujours en cours portent sur la généralisation d'une méthode de conception de composants d'interface matériels à partir <br />d'une spécification sous forme de services requis et fournis. Une telle spécification est déjà utilisée pour représenter des protocoles dans les réseaux de communication et pour le développement<br />des couches logicielles de communication. Son extension à la conception des interfaces matérielles homogénéiserait les langages, méthodes et outils de l'environnement de conception. Mes travaux futurs s'orientent vers deux axes : l'intégration <br />logiciel/matériel et l'adéquation entre architecture et système d'exploitation. Dans les deux cas, les relations étroites entre les ressources physiques de l'architecture et les couches logicielles qui y accèdent doivent permettre d'améliorer sensiblement les performances.

The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing methods, most of which are based on low-level representations of the hardware circuits. Therefore, more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. At the same time, the automatic test equipment based solutions have failed to deliver the required test quality. As a result, alternative testing methods have been studied, which has led to the development of built-in self-test (BIST) techniques. In this thesis, we present a novel hybrid BIST technique that addresses several areas where classical BIST methods have shortcomings. The technique makes use of both pseudorandom and deterministic testing methods, and is devised in particular for testing modern systems-on-chip. One of the main contributions of this thesis is a set of optimization methods to reduce the hybrid test cost while not sacrificing test quality. We have devel oped several optimization algorithms for different hybrid BIST architectures and design constraints. In addition, we have developed hybrid BIST scheduling methods for an abort-on-first-fail strategy, and proposed a method for energy reduction for hybrid BIST. Devising an efficient BIST approach requires different design modifications, such as insertion of scan paths as well as test pattern generators and signature analyzers. These modifications require careful testability analysis of the original design. In the latter part of this thesis, we propose a novel hierarchical test generation algorithm that can be used not only for manufacturing tests but also for testability analysis. We have also investigated the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation. Experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodologies and techniques.

QC 20101018

Abstract The development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those operations demanding stringent security levels but also many daily use consumer applications request the existence of computational platforms in charge of recognizing the identity of one individual based on the analysis of his/her physiological and/or behavioural characteristics. The state of the art points out two main open problems in the implementation of such applications: on the one hand, the needed reliability improvement in terms of recognition accuracy, overall security and real-time performances; and on the other hand, the cost reduction of those physical platforms in charge of the processing. This work aims at finding the proper system architecture able to address those limitations of current personal recognition applications. Embedded system solutions based on hardware-software co-design techniques and programmable (and run-time reconfigurable) logic devices under FPGAs or SOPCs is proven to be an efficient alternative to those existing multiprocessor systems based on HPCs, GPUs or PC platforms in the development of that kind of high-performance applications at low cost / El desenvolupament de sistemes automàtics de reconeixement personal basats en tècniques biomètriques esdevé una realitat en l’era tecnològica actual. No només aquelles operacions que exigeixen un elevat nivell de seguretat sinó també moltes aplicacions quotidianes demanen l’existència de plataformes computacionals encarregades de reconèixer la identitat d’un individu a partir de l’anàlisi de les seves característiques fisiològiques i/o comportamentals. L’estat de l’art de la tècnica identifica dues limitacions importants en la implementació d’aquest tipus d’aplicacions: per una banda, és necessària la millora de la fiabilitat d’aquests sistemes en termes de precisió en el procés de reconeixement personal, seguretat i execució en temps real; i per altra banda, és necessari reduir notablement el cost dels sistemes electrònics encarregats del processat biomètric. Aquest treball té per objectiu la cerca de l’arquitectura adequada a nivell de sistema que permeti fer front a les limitacions de les aplicacions de reconeixement personal actuals. Es demostra que la proposta de sistemes empotrats basats en tècniques de codisseny hardware-software i dispositius lògics programables (i reconfigurables en temps d’execució) sobre FPGAs o SOPCs resulta ser una alternativa eficient en front d’aquells sistemes multiprocessadors existents basats en HPCs, GPUs o plataformes PC per al desenvolupament d’aquests tipus d’aplicacions que requereixen un alt nivell de prestacions a baix cost. / El desarrollo de sistemas automáticos de reconocimiento personal basados en técnicas biométricas se ha convertido en una realidad en la era tecnológica actual. No tan solo aquellas operaciones que requieren un alto nivel de seguridad sino también muchas otras aplicaciones cotidianas exigen la existencia de plataformas computacionales encargadas de verificar la identidad de un individuo a partir del análisis de sus características fisiológicas y/o comportamentales. El estado del arte de la técnica identifica dos limitaciones importantes en la implementación de este tipo de aplicaciones: por un lado, es necesario mejorar la fiabilidad que presentan estos sistemas en términos de precisión en el proceso de reconocimiento personal, seguridad y ejecución en tiempo real; y por otro lado, es necesario reducir notablemente el coste de los sistemas electrónicos encargados de dicho procesado biométrico. Este trabajo tiene por objetivo la búsqueda de aquella arquitectura adecuada a nivel de sistema que permita hacer frente a las limitaciones de los sistemas de reconocimiento personal actuales. Se demuestra que la propuesta basada en sistemas embebidos implementados mediante técnicas de codiseño hardware-software y dispositivos lógicos programables (y reconfigurables en tiempo de ejecución) sobre FPGAs o SOPCs resulta ser una alternativa eficiente frente a aquellos sistemas multiprocesador actuales basados en HPCs, GPUs o plataformas PC en el ámbito del desarrollo de aplicaciones que demandan un alto nivel de prestaciones a bajo coste

Application-specific optimization of embedded systems becomes inevitable to satisfy the market demand for designers to meet tighter constraints on cost, performance and power. On the other hand, the flexibility of a system is also important to accommodate the short time-to-market requirements for embedded systems. To compromise these incompatible demands, coarse-grained reconfigurable architecture (CGRA) has emerged as a suitable solution. A typical CGRA requires many processing elements (PEs) and a configuration cache for reconfiguration of its PE array. However, such a structure consumes significant area and power. Therefore, designing cost-effective CGRA has been a serious concern for reliability of CGRA-based embedded systems. As an effort to provide such cost-effective design, the first half of this work focuses on reducing power in the configuration cache. For power saving in the configuration cache, a low power reconfiguration technique is presented based on reusable context pipelining achieved by merging the concept of context reuse into context pipelining. In addition, we propose dynamic context compression capable of supporting only required bits of the context words set to enable and the redundant bits set to disable. Finally, we provide dynamic context management capable of reducing reduce power consumption in configuration cache by controlling a read/write operation of the redundant context words In the second part of this dissertation, we focus on designing a cost-effective PE array to reduce area and power. For area and power saving in a PE array, we devise a costeffective array fabric addresses novel rearrangement of processing elements and their interconnection designs to reduce area and power consumption. In addition, hierarchical reconfigurable computing arrays are proposed consisting of two reconfigurable computing blocks with two types of communication structure together. The two computing blocks have shared critical resources and such a sharing structure provides efficient communication interface between them with reducing overall area. Based on the proposed design approaches, a CGRA combining the multiple design schemes is shown to verify the synergy effect of the integrated approach. Experimental results show that the integrated approach reduces area by 23.07% and power by up to 72% when compared with the conventional CGRA.

For the on-chip bus, flexibility is the key to reuse by enabling developers to select the optimal architecture to efficiently meet the performance requirements of a wide variety of systems. AMBA is an open standard, on-chip bus specification that details a strategy for the interconnection and management of functional blocks that makes up a System-on-Chip (SoC). AMBA will let designers multiply the total bandwidth available in a system without changing the bus interface on existing intellectual property (IP) cores. Sometimes, the SoC designer to select the optimal combination of bus frequency (to match the peripherals) and number of channels (to achieve the bandwidth), using the AMBA Multi-layer architecture. The AHB of the AMBA System Bus connects embedded processors such as an ARM core to high-performance peripherals, DMA controllers, on-chip memory and interfaces. It is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance. In this thesis, we implement an software, Automatic Generation of On-Chip Bus Infrastructure for SoC, and it supports the AMBA AHB, Multi-layer AHB architecture to optimize system bandwidth, or AHB-Lite to streamline single master layers. By user set up, it can generate the relative on-chip bus infrastructure. We use each AHB Monitor of SDV and Synposys to validate the protocol of infrastructure respectively. In Test Patterns, we use Bus Functional Model to verify all type transfers of bus. In hardware implement, we use SYS32TM, SYS32TME, SYS16TM, and MEMCU to integrate three type AHBs. Every example, we also build FPGA prototyping and chip layout. We do this to validate our on-chip bus infrastructure.

No description available.