Advances in microelectronics technology have enabled us to integrate a complex electronic system (such as a radio) on a single chip or in a single package module, known as system-on-chip (SoC) and system-on-package (SoP) paradigms. This brings not only new opportunities for system integration, but also challenges in design and implementation. One of these challenges is how to achieve an optimum total solution of system integration via chip and package co-design, because there is no tool or design methodology available for such kind of optimization. This thesis focuses on innovative multi-band multi-standard radio front-end design and explores a new design methodology. The motivation of developing this design methodology is to achieve an optimum total solution for radio system implementation via chip and package co-design and co-optimization. The methodology starts from RF packaging and components modeling. Necessary models for both on-chip and off-chip passives are developed. Parasitic effects of packages for radio chips are modeled for particular frequencies. Compared with high-speed digital packaging, RF packaging normally deals with narrow band signals. It is possible to absorb some unwanted parasitics by designing proper port matching networks. In addition, cost-performance trade-offs are performed. In this context, we first developed process and technology based cost models, which include parameters like chip real estate, raw materials, package, test and rework. Impact of process variation on final yield has also been considered in the models by using a statistical analysis approach. Performance of different design options is measured by a special FoM (figure-of-merit). Each type of analog/RF circuit (such as LNA, PA and ADC) has its own dedicated FoM. Through a series of cost-performance trade-offs for different on-chip versus off-chip passives and partitions, an optimum total solution is obtained. Finally, this methodology was demonstrated via a number of design examples for multi-band multi-standard radio front-end. The author has explored the optimum solutions for different circuit architectures and process technologies encompassing parallel, concurrent and digitally programmable multi-band radio frond-end blocks. It is interesting to find that, for complex RF circuits like a multi-band multi-standard radio, moving some passives off-chip will have significant cost-savings. In addition to the above contributions, the author has also developed an MCM-D technology on LCP and glass substrates, based on metal deposition and BCB spin-coating at KTH clean room. The author has also performed some preliminary studies on UWB radio for RFID applications. / QC 20101005

QC 20101018

No description available.

Continued technology scaling together with the integration of disparate technologies in a single chip means that device performance continues to outstrip interconnect and packaging capabilities, and hence there exist many difficult engineering challenges, most notably in power management, noise isolation, and intra and inter-chip communication. Significant research effort spanning many decades has been expended on traditional VLSI integration technologies, encompassing process, circuit and architectural issues to tackle these problems. Recently however, three- dimensional (3-D) integration has emerged as a leading contender in the challenge to meet performance, heterogeneous integration, cost, and size demands through this decade and beyond. Through silicon via (TSV) based 3-D wafer-level integration is an emerging vertical interconnect methodology that is used to route the signal and power supply links through all chips in the stack vertically. Delay and signal integrity (SI) calculation for signal propagation through TSVs is a critical analysis step in the physical design of such systems. In order to reduce design time and mirror well established practices, it is desirable to carry this out in two stages, with the physical structures being modelled by parasitic parameters in equivalent circuits, and subsequent analysis of the equivalent circuits for the desired metric. This thesis addresses both these issues. Parasitic parameter extraction is carried out using a field solver to explore trends in typical technologies to gain an insight into the variation of resistive, capacitive and inductive parasitics including coupling effects. A set of novel closed-form equations are proposed for TSV parasitics in terms of physical dimensions and material properties, allowing the electrical modelling of TSV bundles without the need for computationally expensive field-solvers. Suitable equivalent circuits including capacitive and inductive coupling are derived, and comparisons with field solver provided values are used to show the accuracy of the proposed parasitic parameter models for the purpose of performance and SI analysis. The deep submicron era saw the interconnection delay rather than the gate delay become the major bottleneck in modern digital design. The nature of this problem in 3-D circuits is studied in detail in this thesis. The ubiquitous technique of repeater insertion for reducing propagation delay and signal degradation is examined for TSVs, and suitable strategies and analysis techniques are proposed. Further, a minimal power smart repeater suitable for global on-chip interconnects, which has the potential to reduce power consumption by as much as 20% with respect to a traditional inverter is proposed. A modeling and analysis methodology is also proposed, that makes the smart repeater easier to amalgamate in CAD flows at different levels of hierarchy from initial signal planning to detailed place and route when compared to alternatives proposed in the literature. Finally, the topic of system-level performance estimation for massively integrated systems is discussed. As designers are presented with an extra spatial dimension in 3-D integration, the complexity of the layout and the architectural trade-offs also increase. Therefore, to obtain a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. This thesis presents a cohesive analysis of the technological, cost, and performance trade-offs for digital and mixed-mode systems, outlining the choices available at different points in the design and their ramifications / QC 20100916

Afin d'étendre la diversité des composants intégrables dans un System in Package (SiP), il apparaît nécessaire de développer l'intégration de composants hétérogènes. Cette étude présente une solution par report avec un scellement en polymère. L'utilisation de ces matériaux entraîne des problèmes de fiabilité thermomécanique. Grâce à un prototype virtuel, il est possible d'évaluer les sollicitations et de comprendre ce comportement de la structure. Cela permet de mieux appréhender les mécanismes de défaillance et d'optimiser la structure avant sa fabrication. Pour démontrer la faisabilité, nous avons utilisé des filtres à ondes acoustiques de surfaces (SAW filters). Nous avons étudié trois types de polymères (BCB, SU8 et TMMF) pour réaliser le scellement et protéger le filtre. Différents tests mécaniques, électriques et de fiabilité ont permis de valider cette solution. Nous avons réalisé un SiP comprenant un tuner et un filtre SAW dans un même boîtier pour de la télévision sur mobile

The integration of mixed-signal systems has long been a problem in the semiconductor industry. CMOS System-on-Chip (SOC), the traditional means for integration, fails mixed-signal systems on two fronts; the lack of on-chip passives with high quality (Q) factors inhibits the design of completely integrated wireless circuits, and the noise coupling from digital to analog circuitry through the conductive silicon substrate degrades the performance of the analog circuits. Advancements in semiconductor packaging have resulted in a second option for integration, the System-On-Package (SOP) approach. Unlike SOC where the package exists just for the thermal and mechanical protection of the ICs, SOP provides for an increase in the functionality of the IC package by supporting multiple chips and embedded passives. However, integration at the package level also comes with its set of hurdles, with significant research required in areas like design of circuits using embedded passives and isolation of noise between analog and digital sub-systems. A novel multiband balun topology has been developed, providing concurrent operation at multiple frequency bands. The design of compact wideband baluns has been proposed as an extension of this theory. As proof-of-concept devices, both singleband and wideband baluns have been fabricated on Liquid Crystalline Polymer (LCP) based organic substrates. A novel passive-Q based optimization methodology has been developed for chip-package co-design of CMOS Low Noise Amplifiers (LNA). To implement these LNAs in a mixed-signal environment, a novel Electromagnetic Band Gap (EBG) based isolation scheme has also been employed. The key contributions of this work are thus the development of novel RF circuit topologies utilizing embedded passives, and an advancement in the understanding and suppression of signal coupling mechanisms in mixed-signal SOP-based systems. The former will result in compact and highly integrated solutions for RF front-ends, while the latter is expected to have a significant impact in the integration of these communication devices with high performance computing.

The investigation of liquid crystal polymer (LCP) technology to function as a low-cost next-generation organic platform for designs up to millimeter-wave frequencies has been performed. Prior to this research, the electrical performance of LCP had been characterized only with the implementation of standard transmission lines and resonators. In this research, a wide variety of passive functions have been developed on LCP technology and characterized for the first time. Specifically, we present the development of patch antenna arrays for remote sensing applications, the performance of compact low-pass and band-pass filters up to millimeter-wave frequencies, and the integration of passive elements for X-band and V-band transceiver systems. First, dual-frequency/dual-polarization antenna arrays have been developed on multilayer LCP technology and have been integrated with micro-electro-mechanical-system (MEMS) switches to achieve real-time polarization reconfigurability. These arrays are conformal, efficient and have all the features desirable for applications that require space deployment. Second, a wide variety of filters with different physical and functional characteristics have been implemented on both single and multilayer LCP technology. These filters can be classified based on the filter type (low-pass/band-pass), the resonators used (single-mode/dual-mode), the response characteristics (symmetric/asymmetric), and the structure of the filter (modular/non-modular). Last, examples of integrated modules for use in transceiver systems are presented. This part of the research involves the development of duplexers, radiating elements, as well as their integration. The duplexers themselves are realized by integrating a set of band-pass filters and matching networks. The characterization of the individual components, and of the integrated system are included. This research has resulted in a thorough understanding of LCP's electrical performance and its multilayer lamination capabilities pertaining to its functioning as a material platform for integrated microwave systems. Novel passive prototypes that can take advantage of such multilayer capabilities have been developed.

The objective of the proposed research is to present a compact system-on-package (SOP)-based passive front-end solution for millimeter-wave wireless communication/sensor applications, that consists of fully integrated three dimensional (3D) cavity filters/duplexers and antenna. The presented concept is applied to the design, fabrication and testing of V-band transceiver front-end modules using multilayer low temperature co-fired (LTCC) technology. The millimeter-wave front-end module is the foundation of 60 GHz (V-band) wireless systems for short-range multimedia applications, such as high-speed internet access, video streaming and content download. Its integration poses stringent challenges in terms of high performance, large number of embedded passive components, low power consumption, low interference between integrated components and compactness. To overcome these major challenges, a high level of integration of embedded passive functions using low-cost and high-performance materials that can be laminated in 3D, such as the multilayer LTCC, is significantly critical in the module-level design. In this work, various compact and high-performance passive building blocks have been developed in both microstrip and cavity configurations and their integration, enabling a complete passives integration solution for 3D low-cost wireless millimeter-wave front-end modules. It is worthy to note that most of the designs implemented comes away with novel ideas and is presented as the first extensive state-of-art components, entirely validated by measured data at 60 GHz bands.

The goal of the research in this dissertation is to design and characterize embedded passive components, interconnects, and circuits in inhomogeneous, multi-layer liquid crystalline polymer (LCP) substrates. The attenuation properties of inhomogeneous multi-layer LCP substrates were extracted up to 40 GHz. This is the first result for an inhomogeneous LCP stack-up that has been reported. The characterization results show excellent loss characteristics, much better than FR-4-based technology, and they are similar to LTCC and homogeneous LCP-based technology. A two-port characterization method based on measurements of multiple arrays of vias is proposed. The method overcomes the drawbacks of the one-port and other two-port characterizations. Model-to-hardware correlation was verified using multi-layer model in Agilent ADS and measurement-based via model using arrays of the vias. The resulting correlations show that this method can be readily applied to other vertical interconnect structures besides via structures. Comprehensive characterizations have been conducted for the efficient 3D integration of high-Q passives using a balanced LCP substrate. At two different locations from three different large M-LCP panels, 76 inductors and 16 3D capacitors were designed and measured. The parameters for the measurement-based inductor model were extracted from the measured results. The results validate the large panel process of the M-LCP substrate. To reduce the lateral size, multi-layer 3D capacitors were designed. The designed 3D capacitors with inductors can provide optimized solutions for more efficient RF front-end module integration. In addition, the parameters for the measurement-based capacitor model were extracted. Various RF front-end modules have been designed and implemented using high-Q embedded passive components in inhomogeneous multi-layer LCP substrates. A C-band filter using lumped elements has been designed and measured. The lumped baluns were used to design a double balnced-mixer for 5 GHz WLAN application and a doubly double-balanced mixer for 1.78 GHz CDMA receiver miniaturization. Finally, to overcome the limitations of the lumped component circuits, a 30 GHz gap-coupled band-pass filter in inhomogeneous multi-layer LCP substrates, and the measured results using SOLT and TRL calibrations have been compared to the simulation results.

This thesis describes the architecture, verification, qualification, and packaging of a 16-channel silicon-germanium (SiGe) Remote Electronics Unit (REU) designed for use in extreme environment applications encountered on NASA's exploration roadmap. The SiGe REU was targeted for operation outside the protective electronic "vaults" in a lunar environment that exhibits cyclic temperature swings from -180ºC to 120ºC, a total ionizing dose (TID) radiation level of 100 krad, and heavy ion exposure (single event effects) over the mission lifetime. The REU leverages SiGe BiCMOS technological advantages and design methodologies, enabling exceptional extreme environment robustness. It utilizes a mixed-signal Remote Sensor Interface (RSI) ASIC and an HDL-based Remote Digital Control (RDC) architecture to read data from up to 16 sensors using three different analog channel types with customizable gain, current stimulus, calibration, and sample rate with 12-bit analog-to-digital conversion. The SiGe REU exhibits excellent channel sensitivity throughout the temperature range, hardness to at least 100 krad TID exposure, and single event latchup immunity, representing the cutting edge in cold-capable electronic systems. The SiGe REU is the first example within a potential paradigm shift in space-based electronics.