<p>The technical evolution during the past decade have escalated the use of electronic devices, which are more common today than ever before. The market is still growing rapidly and will continue to do so. The reason for this is the increased demand for devices with integrated circuits. In addition to the increased volume of production, the chips are also becoming more complex which is also reflected in the requirements of the chip design process.</p><p>An advanced chip that combines several different hardware modules (cores) to form a complete system is called a System-on-Chip (SoC). It is of great importance that these chips work according to expectation, although it can be difficult to guarantee. The purpose of SoC testing is to verify correct behaviour as well as for diagnosis and debug.</p><p>Complex systems lead to more and bigger tests which lead to increased test data volume and test time. This results in a higher test cost and many methods are proposed to remedy this situation.</p><p>This report proposes a method that minimises fail result data with a real-time compression component embedded on the chip. The compressed fail results can be saved on-chip and retrieved when needed instead of during the test.</p><p>Furthermore this method will facilitate debug and diagnosis of SoCs. A mask buffer is used to give the opportunity of choosing exactly which cycles, pins or bits that are relevant. All other result bits are masked and ignored.</p><p>The results are satisfying, the data is compressed to a much smaller size which is easier to store on-chip. The method is simple, fast and loss-less.</p>

Zugl.: Zürich, Techn. Hochsch., Diss.

Zugl.: München, Techn. Univ., Diss., 2009

ITC/USA 2014 Conference Proceedings / The Fiftieth Annual International Telemetering Conference and Technical Exhibition / October 20-23, 2014 / Town and Country Resort & Convention Center, San Diego, CA / This paper describes a system framework for a multi-band, multi-mode software defined radio (MBMM SDR) being developed for next-generation telemetry applications. The system framework consists of the multi-band front-end (MBFE), the multi-mode digital radio (MMDR), and the configuration and control (C2) sub-systems. The MBFE consists of an L/S/C-band transceiver architecture that provides wideband operation, band selection, and channel tuning. The MMDR consists of the software and firmware components for high-speed digital signal processing for the telemetry waveforms. Finally, the C2 consists of the software and hardware components for system configuration, control and status. The MBFE is implemented as a standalone hardware sub-system, while the MMDR and C2 are integrated into a single hardware subsystem that utilizes state-of-the-art system-on-chip (SoC) technology. Design methodologies, hardware architectures, and system tradeoffs are highlighted to meet next-generation telemetry requirements for improved spectrum efficiency and utilizations. Approved for public release; distribution is unlimited (412TW-PA-14281).

The aggressive scaling of the semiconductor technology following the Moore’s Law has delivered true system-on-chip (SoC) integration. Network-on-chip (NoC) has been recently introduced as an effective solution for scalable on-chip communication since dedicated point-to-point (P2P) interconnection and shared bus architecture become performance and power bottlenecks in the SoCs. This dissertation studies three critical NoC challenges such as latency, power, and compatibility with emerging technologies in aspect of an architecture and physical design level. Latency is a key issue in NoC since the performance of applications considerably depends on resource sharing policies employed in an on-chip network. NoCs have been mainly developed to improve network-level performance that captures the inherent performance characteristics of a network itself, but the network-level optimizations are not directly related to application- or system-level performance. In addition, memory latency on NoC critically affects the performance of applications or systems. We propose a synchronous dynamic random access memory (SDRAM) aware NoC design to optimize memory throughput, latency, and design complexity. Furthermore, it is extended to an application-aware NoC design to provide the quality-of-service (QoS) of memory for various applications. NoC provides great on-chip communication. However, it brings no true relief to power budget when the on-chip network scales in terms of complexity/size and signal bandwidth. The combination of NoC and other techniques has the potential to reduce power. We study two power saving research topics for NoC: (a) we propose a voltage-frequency island (VFI) aware NoC optimization framework with a better tradeoff between power efficiency and design complexity to minimize both computation and on-chip communication power. (b) We formulate an application mapping problem to mixed integer quadratic programming (MIQP) with the purpose of reducing power consumption in various hard networks and develop highly efficient algorithms for the MIQP. Regarding NoC compatible with new technologies, we focus on three dimensional (3D) die integration based on through-silicon vias (TSVs). Since an on-chip network design has been subject to not only application constraints but also design/manufacturing constraints, a 3D NoC design is required for innovation in interconnection networks. We propose a chemical-mechanical polishing (CMP) aware application-specific 3D NoC design that minimizes TSV height variation, thus reduces bonding failure, and meanwhile optimizes conventional NoC design objectives such as hop count, wirelength, power, and area. / text

Nowadays, there is a growing demand for high frequency-bandwidth mm-wave (30-300 GHz) electronic wireless transceiver systems to support applications such as high data-rate wireless communication and high resolution imaging. Such mm-wave systems are becoming more feasible due to the extreme transistor downscaling in silicon-based integrated circuits, which enabled densely-integrated high-speed elec- tronics operating up to more than 100 GHz with low fabrication cost. To further enhance system integrability, it is required to implement all wireless system compo- nents on the chip. Presently, the last major barrier to true System-on-Chip (SoC) realization is the antenna implementation on the silicon chip. Although at mm-wave frequencies the antenna size becomes small enough to fit on chip, the antenna performance is greatly deteriorated due the high conductivity and high relative permittivity of the silicon substrate. The negative e↵ects of the silicon substrate could be avoided by using a metallic reflecting surface on top of silicon, which e↵ectively isolates the antenna from the silicon. However, this approach has the shortcoming of having to implement the antenna on the usually very thin silicon oxide layer of a typical CMOS fabrication process (10’s of μm). This forces the antenna to be in a very close proximity (less than one hundredth of a wavelength) to the reflecting surface. In this regime, the use of conventional metallic reflecting surface for silicon shielding has severe e↵ects on the antenna performance as it tends to reduce the antenna radiation resistance resulting in most of the energy being absorbed rather than radiated. In this work, the use of specially patterned reflecting surfaces for improving on- chip antenna performance is investigated. By using a periodic metallic surface on top of a grounded substrate, the structure can mimic the behavior of a perfect mag- netic conductor, hence called Artificial Magnetic Conductor (AMC) surface. Unlike conventional ground plane reflecting surfaces, AMC surfaces generally enhance the radiation and impedance characteristics of close-by antennas. Based on this property, a ring-based AMC reflecting surface has been designed in the oxide layer for on-chip antennas operating at 94 GHz. Furthermore, a folded dipole antenna with its associ- ated planar feeding structures has been optimized and integrated with the developed ring-based AMC surface. The proposed design is then fabricated at KAUST clean- room facilities. Prototype characterization showed very promising results with good correlation to simulations, with the antenna exhibiting an impedance bandwidth of 10% (90-100 GHz) and peak gain of -1.4 dBi, which is the highest gain reported for on-chip antennas at this frequency band without the use of any external o↵-chip components or post-fabrication steps.

As the number of processors in multiprocessor system-on-chip devices continues to increase, the complexity required for full cache coherence support is often unwarranted for application-specific designs. Bus-based interconnects are no longer suitable for larger-scale systems, and the logic and storage overhead associated with the use of a complex packet-switched network and directory-based cache coherence may be undesirable in single-chip systems. Unidirectional rings are a suitable alternative because they offer many properties favorable to both on-chip implementation and to supporting cache coherence. Reducing the overhead of cache coherence traffic is, however, a concern for these systems. This thesis adapts two filter structures that are based on principles of coarse-grained coherence tracking, and applies them to a ring-based multiprocessor. The first structure tracks the total number of blocks of remote data cached by all processors in a node for a set of regions, where a region is a large area of memory referenced by the upper bits of an address. The second structure records regions of local data whose contents are not cached by any remote node. When used together to filter incoming or outgoing requests, these structures reduce the extent of coherence traffic and limit the transmission of coherent requests to the necessary parts of the system. A complete single-chip multiprocessor system that includes the proposed filters is designed and implemented in programmable logic for this thesis. The system is composed of nodes of bus-based multiprocessors, and each node includes a common memory, two or more pipelined 32-bit processors with coherent data caches, a split-transaction bus with separate lines for requests and responses, and an interface for the system-level ring interconnect. Two coarse-grained filters are attached to each node to reduce the impact of coherence traffic on the system. Cache coherence within the node is enforced through bus snooping, while coherence across the interconnect is supported by a reduced-complexity ring snooping protocol. Main memory is globally shared and is physically distributed among the nodes. Results are presented to highlight the system's key implementation points. Synthesis results are presented in order to evaluate hardware overhead, and operational results are shown to demonstrate the functionality of the multiprocessor system and of the filter structures. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-10-24 10:16:47.81 / Financial support for this work was provided by the National Sciences and Engineering Research Council of Canada, Communications and Information Technology Ontario, and Queen's University.

In this thesis, an 8-bit microcontroller, 8051 core, is implemented using SystemC programming language. SystemC is a new generation co-design language which is capable of both programming software and describing hardware parts of a complete system. The benefit of this design environment appears while developing a System-on-Chip (SoC), that is a system consisting both custom hardware parts and embedded software parts. SystemC is not a completely new language, but based on C++ with some additional class libraries and extensions to handle hardware related concepts such as signals, multi-valued logic, clock and delay elements. 8051 is an 8 bit microcontroller which is widely used in industry for many years. The 8051 core is still being used as the main controller in today&rsquo / s highly complex chips, such as communication and bus controllers. During the development cycles of a System-on-Chip, instead of using separate design environments for hardware and software parts, the usage of a unified co-design environment provides a better design and simulation methodology which also decreases the number of iterations at hardware software integration. In this work, an 8-bit 8051 microcontroller core and external memory modules are developed using SystemC that can be re-used in future designs to achieve more complex System-on-Chip&rsquo / s. During the development of the 8051 core, simulation results are analyzed at each step to verify the design from the very beginning of the work, which makes the design processes more structured and controlled and faster as a result.

The ubiquity of Internet connectivity means there is a greater need for computer network safety and security. Cost-effective secure computing networks and broadband applications not only need a sophisticated cryptosystem to accelerate data encryption, but also need substantial computational power to handle large data streams. Reconfigurable System-on-Chip (rSoC) technology is well suited to accelerate network cryptographic applications by implementing the entire computing application on a single reconfigurable chip. Hardware-software co-design and hardware-software communication are some key questions involved in using this rSoC technology. This thesis investigates how best to accelerate a cryptographic application using rSoC technology. Some background on FPGAs, reconfigurable computing, inter-process communication methods, hardware/software co-design, cryptography in general, and 3DES in particular are firstly introduced. Some existing reconfigurable computing systems and 3DES implementations on FPGA are then reviewed and analyzed. A new general hardware-software architecture, which consists of a CPU, memories, customized peripherals and buses on a single FPGA chip, is designed to accelerate the security application. The 3DES application is divided into four functional modules: input, subkey generation, data processing, and output modules. Shared memory with semaphores is chosen for the inter-module communication. A complete inter-module communication solution is presented for hardware and software module communications. A generic component, HWCOM, is designed for those communications which involve hardware modules. Experimental results show that using two buffers as shared memories between communication modules and increasing shared memory size are good methods for transferring data between hardware/software modules more efficiently. When investigating the best hardware/software partition scheme, all 3DES modules are first executed in software on the FPGA. The experimental results of 83Kbps encryption throughput indicate that the software-only solution is not satisfactory. Through profiling, the bottleneck is shown to be the data processing module and the subkey generation module, which are then implemented in hardware. Experimental results show an improved 179Mbps throughput. This presents over 2000 times acceleration compared to software and shows that the hardware-software co-implementation can efficiently accelerate the 3DES application with good performance and flexibility.

Zugl.: Erlangen, Nürnberg, Univ., Diss., 2006