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Thermal management has emerged as an important design issue in a range of designs from portable devices to server systems. Internal thermal sensors are an integral part of such a management system. Process variations in CMOS circuits cause accuracy problems for thermal sensors which can be fixed by calibration tables. Stand-alone thermal sensors are calibrated to fix such problems. However, calibration requires going through temperature steps in a tester, increasing test application time and cost. Consequently, calibrating thermal sensors in typical digital designs including mainstream desktop and notebook processors increases the cost of the processor. This creates a need for design of thermal sensors whose accuracy does not vary significantly with process variations. Other qualities desired from thermal sensors include low area requirement so that many of them maybe integrated in a design as well as low power dissipation, such that the sensor itself does not become a significant source of heat. In this work, we developed a process variation tolerant thermal sensor design with (i) active compensation circuitry and (ii) signal dithering based self calibration technique to meet the above requirements in 32nm technology. Results show that we achieve 3ºC temperature accuracy, with a relatively small design which compares well with designs that are currently used.

This thesis describes an accurate and scalable computational method designed to perform nanoelectronic structure calculations. Built around the FEAST framework, this method directly addresses the nonlinear eigenvalue problem. The new approach allows us to bypass traditional approximation techniques typically used for first-principle calculations. As a result, this method is able to take advantage of standard muffin-tin type domain decomposition techniques without being hindered by their perceived limitations. In addition to increased accuracy, this method also has the potential to take advantage of parallel processing for increased scalability. The Introduction presents the motivation behind the proposed method and gives an overview of what will be presented for this thesis. Chapter 1 explains how electronic structure calculations are currently performed, including an overview of Density Functional Theory and the advantages and disadvantages of various numerical techniques. Chapter 2 describes, in detail, the method proposed for this thesis, including mathematical justification, a matrix-level example, and a description of implementing the FEAST algorithm. Chapter 3 presents and discusses results from numerical experiments for Hydrogen and various Hydrogen molecules, Methane, Ethane, and Benzene. Chapter 4 concludes with a summary of the presented work and its impact in the field.

Over the last five years, charge-coupled devices (CCD) have been improved dramatically in terms of sensitivity, manufacturability and particularly, cost. This has enabled them to be used economically in many more industrial and commercial electronic imaging processes. They are found in products ranging from video cameras to satellite-based camera systems. This has sparked my interests in these devices, and with a great deal of encouragement from Dr. Turpin, I decided to base my Master's thesis/project on a CCD. The project was mainly based on the design of the electronics and optics needed to support a CCD. The particular circuit design which I used other designs which are available. Many of the designs are microprocessor- based, which tends to limit the speed of operation of the imaging process. Other circuits employ specially coded memory chips to implement the required logic processes, but again, the speed of operation is limited by the access times of the memory chips. The circuit employed in the project uses only logic gates and flip flops, and is probably one of the fastest circuits available for the capture of single-frame images.

Falls in the disabled and elderly people have been a cause of concern as they can be immobilized by the fall and have no way to contact others and seek assistance. The proposed frequency modulated continuous wave (FMCW) short range radar (SRR) system, which uses ultra-wideband (UWB) signals can provide immediate assistance by monitoring and detecting fall events. The unique characteristics of this system allow for a frequency-based modulation system to carry out triangulation and sense the location of the fall through the usage of a continuous chirp signal that linearly sweeps frequency. This project focuses on the development, design and simulation of a ring oscillator that exhibits the frequency modulated signal on a single integrated circuit chip. The ring oscillator is controlled by a voltage ramp signal generator and a voltage to current (V-I) converter. The circuit is designed in Cadence using TSMC 180nm process technology and operates in the frequency range of 3.409 GHz to 5.349 GHz with a spectral bandwidth of 1.94 GHz, which meets the Federal Communications Commission’s standards for unlicensed ultra-wideband transmissions.

The number of mobile wireless devices on the market has increased substantially over the last decade. The frequency spectrum has become crowded due to the number of devices demanding radio traffic and new modulation schemes have been developed to accommodate the number of users. These new modulation schemes have caused very poor efficiencies in power amplifiers for wireless transmission systems due to high peak-to-average power ratios (PAPR). This thesis first presents the issue with classical power amplifiers in modern modulation systems. A brief overview of current attempts to mitigate this issue is provided. A new RF power amplifier topology is then presented with supporting simulations. The presented amplifier topology utilizes the concept of negative conductance and load modulation. The amplifier operates in two stages, a low power stage and a high power stage. A negative conductance amplifier is utilized during peak power transmission to modulate the load presented to the input amplifier. This topology is shown to greatly improve the power added efficiency of power amplifiers in systems with high PAPR.

Printed Circuit Boards (PCBs) are a ubiquitous element of virtually every electronic system manufactured world-wide. It is not a stretch of the imagination to say that if it’s electronic, there is a PCB in it. PCBs are necessary tools for electronics work, and tools need to have instructions. For better or worse, PCB knowledge is a deep and wide ocean. There is much to cover for even a surface level understanding, and there are deep areas rich in technical expertise. Navigating the ocean of knowledge is treacherous; common knowledge of yore can be downright dubious now. PCB manufacturing and electronics as a whole have seen incredible developments in the past few decades, and knowledge once true may be outdated. At the same time there is a downpour of new techniques to use and challenges to face. The storm of information deepens the sea and can make it seem impossible to get anywhere without getting utterly lost. There are islands of knowledge out there hiding in books and papers and websites, but no guide to get anywhere. This thesis aims to guide the reader through the sea of information and provides a map that charts the shallows of beginner knowledge, into the deep depths of advanced design, of how and where to learn more. This thesis serves as an aiding means through the exciting and vast world of PCB design and layout.

As the scaling of CMOS approaches fundamental limits, revolutionary technology beyond the end of CMOS roadmap is essential to continue the progress and miniaturization of integrated circuits. Recent research efforts in 3-D circuit integration explore pathways of continuing the scaling by co-designing for device, circuit, connectivity, heat and manufacturing challenges in a 3-D fabric-centric manner. SkyBridge fabric is one such approach that addresses fine-grained integration in 3-D, achieves orders of magnitude benefits over projected scaled 2-D CMOS, and provides a pathway for continuing scaling beyond 2-D CMOS. However, SkyBridge fabric utilizes only single type transistors in order to reduce manufacture complexity, which limits its circuit implementation to dynamic logic. This design choice introduces multiple challenges for SkyBridge such as high switching power consumption, susceptibility to noise, and increased complexity for clocking. In this thesis we propose a new 3-D fabric, similar in mindset to SkyBridge, but with static logic circuit implementation in order to mitigate the afore-mentioned challenges. We present an integrated framework to realize static circuits with vertical nanowires, and co-design it across all layers spanning fundamental fabric structures to large circuits. The new fabric, named as SkyBridge-CMOS, introduces new technology, structures and circuit designs to meet the additional requirements for implementing static circuits. One of the critical challenges addressed here is integrating both n-type and p-type nanowires. Molecular bonding process allows precise control between different doping regions, and novel fabric components are proposed to achieve 3-D routing between various doping regions. Core fabric components are designed, optimized and modeled with their physical level information taken into account. Based on these basic structures we design and evaluate various logic gates, arithmetic circuits and SRAM in terms of power, area footprint and delay. A comprehensive evaluation methodology spanning material/device level to circuit level is followed. Benchmarking against 16nm 2-D CMOS shows significant improvement of up to 50X in area footprint and 9.3X in total power efficiency for low power applications, and 3X in throughput for high performance applications. Also, better noise resilience and better power efficiency can be guaranteed when compared with original SkyBridge fabrics.

<p>We propose a physically based model that describes the density and size of voids in silicon introduced via high dose helium ion implantation and subsequent annealing. The model takes into account interactions between vacancies, interstitials, small vacancy clusters, and voids. Void evolution in silicon occurs mainly by a migration and coalescence process. Various factors such as implantation energy and dose, anneal temperature, atmospheric pressure, and impurity level in silicon can influence the migration and coalescence mechanism and thus play a role in the void evolution process. Values for model parameters are consistent with known values for point defect parameters and assumed diffusion limited reaction rates. A single “fitting parameter” represents the rate of bubble migration and coalescence and is therefore related to surface diffusion of adatoms. Results obtained from simulations based upon the model were compared to our experimental results and to previously reported experimental results obtained over a wide range of conditions.</p> <p>Our own experiments involved the implantation of silicon samples and samples with a thin Si_1-xGe_x (x = 0.05, 0.09) epilayer on silicon with 30 keV, 5×10¹⁶ cm^-2 helium. Anneals were done in the range 960-1110°C for 15-30 minutes in nitrogen and dry oxygen. Void size distributions were measured from transmission electron microscopy images. Average void diameter and void density values and void size distribution did not show any significant differences between the samples annealed in nitrogen and dry oxygen. However, the presence of Si_1-xGe_x epilayer on silicon resulted in increased average void diameter and reduced average void density when compared with Si samples as well as more selective void size distribution.</p> <p>Data from the literature included experiments with helium ion implantation energies in the range 30 - 300 keV, doses of 1×10¹⁶ - 1×10¹⁷ cm^-2, subsequent annealing temperatures in the range 700 - 1200°C, and annealing duration in the range 15 minutes - 2 hours. Excellent agreement is found between the simulated results and those from reported experiments. The extracted migration and coalescence rate parameter shows an activation energy consistent with surface diffusivity of silicon. It shows a linear dependence on helium dose, and increases with decreased implantation energy, decreased ambient pressure, decreased substrate impurities, increased temperature ramp rate, or increased Ge fraction in cavity layer, all consistent with the proposed physical mechanism. Our mathematical model specifically ignores the long time saturation in void size, although we propose a simple explanation consistent with the physical picture. Similarly, we give physical reasons for a threshold implant dose resulting in the formation of small vacancy clusters during implant. But in modeling void growth we simply show that when such clusters exist voids will evolve according to our model.</p> <p>In our experiments, the presence of a Si_0.95Ge_0.05 epilayer on silicon resulted in retarded B diffusion when compared with Si samples. This phenomenon is correlated to the role of the Si_0.95Ge_0.05 epilayer on silicon in the void evolution mechanism and both are attributed to Ge interdiffusing from the epilayer into the Si bulk. The B diffusion data also allows us to predict conditions for the SiGe epilayer to modify the injection of interstitials from surface during dry oxidizing anneal.</p> / Doctor of Philosophy (PhD)

<p>A glass-clad, slow-light photonic-crystal waveguide is proposed as a solution to sub-bandgap light detection in silicon photonic circuits. Such detection in silicon is perceived as a challenge owing to silicon's indirect band gap and transparency to 1550nm wavelengths, yet is essential for achieving low-cost, high-yield integration with today's microelectronics industry. Photonic crystals can be engineered in such a way as to enhance light-matter interaction over a specific bandwidth via the reduction of the group velocity of the propagating wave (i.e. the slowing of light). The interaction enhanced for light detection in the present work is electron-hole pair generation at defect sites. The intrinsic electric field of a p-i-n junction enables light detection by separating the electron-hole pairs as a form of measurable current. The photonic-crystal waveguides are designed to have bandwidths in the proximity of a wavelength of 1550nm. Refractive indices of over 80 near the photonic-crystal waveguide's Brillouin zone boundary are measured using Fourier transform spectral interferometry and are found to correspond to numerical simulations. Defect-induced propagation loss was seen to scale with group index, from 400dB/cm at a group index of 8 to 1200dB/cm at a group index of 88. Scaling was sublinear, which is believed to be due to the spreading of modal volume at large group index values. Photodetectors were measured to have responsivities as high as 34mA/W near the photonic-crystal waveguide's Brillouin zone boundary for a reverse bias of 20V and a remarkably short detector length of 80um. The fabrication of each device is fully CMOS-compatible for the sake of cost-effective integration with silicon microelectronics.</p> / Master of Applied Science (MASc)