Heterojunctions of CuInSe2 (CIS) nanowires with cadmium sulfide (CdS) were fabricated demonstrating for the first time, vertically aligned nanowires of CIS in the conventional Mo/CIS/CdS stack. These devices were studied for their material and electrical characteristics to provide a better understanding of the transport phenomena governing the operation of heterojunctions involving CIS nanowires. Removal of several key bottlenecks was crucial in achieving this. For example, it was found that to fabricate alumina membranes on molybdenum substrates, a thin interlayer of tungsten had to be inserted. A qualitative model was proposed to explain the difficulty in fabricating anodized aluminum oxide (AAO) membranes directly on Mo. Experimental results were used to corroborate this model. Subsequently, a general procedure to use any material that can be deposited using sputtering or evaporation as a back contact for nanowires grown using AAO templates was developed. Experimental work to demonstrate this by transferring thin AAO templates onto flexible Polyimide (PI) substrates was performed. This pattern transfer approach opens doors for a wide variety of applications on almost any substrate. Any material that can be deposited by physical means can then be used as a back contact. Electron-beam induced deposition using a liquid precursor (LP-EBID) was used to selectively grow preconceived patterns of compound semiconductor (CdS) nanoparticles. Stoichiometric CdS nanoparticle patterns were grown successfully using this method. They were structurally and optically characterized indicating high purity deposits. This approach is promising because it marries the precision of e-beam lithography with the versatility of solution based deposition methods.

New power applications for managing increasingly higher power levels require that more heat be removed from the power transistor channel. Conventional treatments for heat dissipation do not take into account the conversion of excess electron energy into longitudinal optical (LO) phonons, whose associated heat is stored in the channel unless such LO phonons decay into longitudinal acoustic (LA) phonons via a Ridley path. A two dimensional electron gas (2DEG) density of ~5×1012cm-2 in the channel results in a strong plasmon–LO phonon coupling (resonance) and a minimum LO phonon lifetime is experimentally observed, implying fast heat removal from the channel. Therefore, it is desirable to shift the resonance condition to higher 2DEG densities, and thereby higher power levels. The more convenient way to attain the latter is by widening the 2DEG density profile via heterostructure engineering, i.e. by using multiple channel heterostructures. A single channel heterostructure (GaN/AlN/AlGaN), a basic heterostructure used to obtain a 2DEG, exhibits a resonance condition at low 2DEG densities (~0.65×1012 cm-2). Successful widening of the 2DEG density xv profile was predicted by simulation results for two types of multiple (Al)GaN channel heterostructures, i.e. coupled channel GaN/AlN/GaN/AlN/AlGaN and dual channel GaN/AlGaN/AlN/AlGaN. Because of a reduction of carrier confinement, it is experimentally observed that control of the channel is moderate in the case of dual channel heterostructures. On the other hand, carrier confinement provides a better control of the channel in coupled channel heterostructures. Furthermore, unlike in a dual channel heterostructure, alloy scattering does not affect carrier transport properties, which results in a higher cut-off frequency. It was found experimentally that the coupled channel heterostructure successfully reaches resonance condition at a 2DEG density that is 23% higher than in a single channel heterostructure. Multiple channel heterostructures therefore provide a convenient way to shift the plasmon-LO phonon resonance to higher 2DEG densities. However, in our grown heterostructures, high power levels under optimal channel working conditions and minimum heat accumulation, all desirable benefits for the development of high power transistors, were only observed in coupled channel heterostructures.

Cal Poly’s ongoing Energy Harvesting from Exercise Machines (EHFEM) project is a very convenient and cost-effective way for generating DC power from physical exercise and sending it back to the electrical grid as AC power, providing a renewable energy source for the future. The EHFEM project consists of numerous subprojects involving converting different types of exercise machines for power generation. This project is a continuation of one of the previous subprojects, specifically involving an elliptical machine, and focuses on improving system functionality at different machine settings without altering the elliptical user’s experience by selecting a new DC-DC converter design, while keeping the other system components intact. The new proposed DC-DC converter design is based on a non-isolated, PWM-switching single-ended primary inductor converter (SEPIC) topology, as opposed to the resonant zero-current switching/zero-voltage switching (ZCS/ZVS) topology-based off-the-shelf DC-DC converter that the previous project utilized, which had poor system functionality at high physical input levels (greater than 30V input) from the elliptical trainer. This project proves that a PWM-switching SEPIC topology provides a functional DC-DC converter design for DC power generation and inverter interfacing from a dynamic input voltage generator because of its wide input voltage range, high power driving capability and inherent voltage step-up and step-down functions. The proposed DC-DC converter supplies up to 288 watts of power and outputs 36 volts, and simultaneously takes 5-65 volts from its input depending on the elliptical user’s physical input level. This project details the new DC-DC converter’s design and construction processes, compares its topology to other existing DC-DC converter topologies and analyzes unfeasible designs as well as the overall system’s performance when converting the generated DC power to AC power, and documents any potential problems when used for this specific application.

Gallium Nitride (GaN) high electron mobility transistors (HEMTs) are becoming increasingly popular in power amplifier systems as an alternative to bulkier vacuum tube technologies. GaN offers advantages over other III-V semiconductor heterostructures such as a large bandgap energy, a low dielectric constant, and a high critical breakdown field. The aforementioned qualities make GaN a prime candidate for high-power and radiation-hardened applications using a smaller form-factor. Several different types of semiconductor substrates have been considered for their thermal properties and cost-effectiveness, and Silicon (Si) has been of increasing interest due to a balance between both factors. In this thesis, the DC, RF, and thermal characteristics of GaN HEMTs grown on Si-substrates will be investigated through a series of accelerated lifetime experiments. A figure of merit known as the critical voltage is explored and used as the primary means by which the GaN-on-Si devices are electrically strained. The critical voltage is defined as the specific voltage bias by which a sudden change in device performance is experienced due to a deformation of the target GaN HEMT’s epitaxial structure. Literature on the topic details the inevitable formation of pits and cracks localized under the drain-side of the gate contact that promote electrical degradation of the devices via the inverse piezoelectric effect. Characteristic changes in device performance due to high field strain are recorded and physical mechanisms behind observed degraded performance are investigated. The study assesses the performance of roughly 60 GaN-on-Si HEMTs in four experimental settings. The first experiment investigates the critical voltage of the device in the off-state mode of operation and explores device recovery post-stress. The second experiment analyzes alterations in DC and RF performance under varying thermal loads and tracks the dependence of the critical voltage on temperature. The third experiment examines electron trapping within the HEMTs as well as detrapping methodologies. The final experiment links the changes in RF performance induced by high field strain to the small-signal parameters of the HEMT. Findings from the research conclude the existence of process-dependent defects that originate during the growth process and lead to inherent electron traps in unstressed devices. Electron detrapping due to high electric field stress applied to the HEMTs was observed, potentially localized within the AlGaN layer or GaN buffer of the HEMT. The electron detrapping in turn contributed to drain current recovery and increased unilateral performance of the transistor in the RF regime. Thermal experiments resulted in a positive shift in critical voltage, which enhanced gate leakage current at lower gate voltage drives.

Future computing will require significant development in new computing device paradigms. This is motivated by CMOS devices reaching their technological limits, the need for non-Von Neumann architectures as well as the energy constraints of wearable technologies and embedded processors. The first device proposal, an energy-efficient voltage-controlled domain wall device for implementing an artificial neuron and synapse is analyzed using micromagnetic modeling. By controlling the domain wall motion utilizing spin transfer or spin orbit torques in association with voltage generated strain control of perpendicular magnetic anisotropy in the presence of Dzyaloshinskii-Moriya interaction (DMI), different positions of the domain wall are realized in the free layer of a magnetic tunnel junction to program different synaptic weights. Additionally, an artificial neuron can be realized by combining this DW device with a CMOS buffer. The second neuromorphic device proposal is inspired by the brain. Membrane potential of many neurons oscillate in a subthreshold damped fashion and fire when excited by an input frequency that nearly equals their Eigen frequency. We investigate theoretical implementation of such “resonate-and-fire” neurons by utilizing the magnetization dynamics of a fixed magnetic skyrmion based free layer of a magnetic tunnel junction (MTJ). Voltage control of magnetic anisotropy or voltage generated strain results in expansion and shrinking of a skyrmion core that mimics the subthreshold oscillation. Finally, we show that such resonate and fire neurons have potential application in coupled nanomagnetic oscillator based associative memory arrays.

Copper zinc tin sulfide (Cu2ZnSnS4 or CZTS) kesterite compound has attracted much attention in the last years as a new abundant, low cost, and environmentally benign material with desirable optoelectronic properties for Photovoltaic (PV) thin film solar cell applications. Among various synthesis routes for CZTS thin films, sol-gel processing is one of the most attractive routes to obtain CZTS films with superior quality and low cost. In this study, sol-gel sulfurization process parameters for CZTS thin films were systematically investigated to identify the proper process window. In addition, temperature dependent Raman spectroscopy was employed to monitor the CZTS sulfurization process in real time and gain fundamental information about the phase formation and degradation mechanisms of CZTS under the relevant processing conditions. It was found that CZTS thin films with different Cu stoichiometry can be prepared using parts-per-million (ppm) level of hydrogen sulfide (H2S) gas as opposed to high percentage level of H2S (e.g., ≥ 5%) in all previous studies. Samples sulfurized at lower temperatures of ~350°C and 125°C revealed the formation of CZTS phase as confirmed by XRD, Raman micro-spectroscopy, and sheet resistance measurement. Local EDS analysis indicates that CZTS films prepared at those low temperatures have a near-stoichiometric composition and are sometimes accompanied by the formation of Cu2-xS phase(s). Also, stoichiometric and Cu-rich precursor solutions tend to yield CZTS samples with better crystallinity and superior optical properties compared with the Cu-deficient solution. Moreover, in situ Raman monitoring of phase formation of CZTS material was carried out from room temperature up to 350°C in a 100 ppm H2S+4%H2+N2 gas mixture. The results showed that CZTS phase formed in about 30 min via a direct reaction between the metal oxide precursor film and the H2S-H2 gas mixture at an intermediate temperature of 350°C and remained stable upon extended exposure. In comparison, at a lower temperature (170°C), the oxide precursor film had to be reduced first (e.g., in 4% H2/N2 forming gas) and then the CZTS phase emerged. However, continued sulfurization at a lower temperature (e.g., 170°C) led to the disintegration of CZTS and the formation of CuS impurity, which remains stable upon cooling the sample down to room temperature. Furthermore, results of in situ Raman monitoring of CZTS films in an oxygen-rich atmosphere at elevated temperatures up to 600°C suggested that CZTS oxidizes first at ~400°C to form tin oxide (SnO2) and binary sulfides of mainly copper sulfide (Cu2-xS) and zinc sulfide (ZnS). Then, at temperatures higher than 400°C, the remaining sulfides oxidize to form zinc oxide (ZnO). The outcomes of the current study set the directions for optimizing the CZTS film structure and stoichiometry toward developing low cost and high-performance CZTS solar cells in future.

To isolate and study various components of a nuclear reaction, elaborate equipment must be developed to aid in this process. This thesis presents the design and implementation of an ultra-high slew rate Bradbury-Nielsen gate driver circuit with high-voltage input isolation. This design will be used in a multi-pass time-of-flight isomer spectrometer and separator application integrated into an overall instrument called the Oak Ridge Isomer Spectrometer and Separator (ORISS). The output drive signals of this circuit are transmitted through a vacuum feed-through system to supply the necessary signals to the Bradbury-Nielsen gate contained within the vacuum. A differential driving signal with a 100-V magnitude and switching times on the order of nanoseconds is presented in this design. The “on time” of this signal is comparable to the amount of time required for it to transition states, creating complex design constraints. The implementation of this design is based on a 4-layer printed circuit board and the use of commercial off-the-shelf (COTS) components.

In this thesis, we discussed various possibilities of integrating scheduling decisions with information and constraints from Advanced Process Control (APC) systems in semiconductor Manufacturing. In this context, important questions were opened regarding the benefits of integrating scheduling and APC. An overview on processes, scheduling and Advanced Process Control in semiconductor manufacturing was done, where a description of semiconductor manufacturing processes is given. Two of the proposed problems that result from integrating bith systems were studied and analyzed, they are :Problem of Scheduling with Time Constraints (PTC) and Problem of Scheduling with Equipement health Factor (PEHF). PTC and PEHF have multicriteria objective functions.PTC aims at scheduling job in families on non-identical parallel machines with setup times and time constraints.Non-identical machines mean that not all miachines can (are qualified to) process all types of job families. Time constraints are inspired from APC needs, for which APC control loops must be regularly fed with information from metrology operations (inspection) within a time interval (threshold). The objective is to schedule job families on machines while minimizing the sum of completion times and the losses in machine qualifications.Moreover, PEHF was defined which is an extension of PTC where scheduling takes into account the equipement Health Factors (EHF). EHF is an indicator on the state of a machine. Scheduling is now done by considering a yield resulting from an assignment of a job to a machine and this yield is defined as a function of machine state and job state.

To handle potentially large size and complicated nonstationary functional data, we present the wavelet-based methodology in data mining for process monitoring and fault classification. Since traditional wavelet shrinkage methods for data de-noising are ineffective for the more demanding data reduction goals, this thesis presents data reduction methods based on discrete wavelet transform. Our new methods minimize objective functions to balance the tradeoff between data reduction and modeling accuracy. Several evaluation studies with four popular testing curves used in the literature and with two real-life data sets demonstrate the superiority of the proposed methods to engineering data compression and statistical data de-noising methods that are currently used to achieve data reduction goals. Further experimentation in applying a classification tree-based data mining procedure to the reduced-size data to identify process fault classes also demonstrates the excellence of the proposed methods. In this application the proposed methods, compared with analysis of original large-size data, result in lower misclassification rates with much better computational efficiency. This thesis extends the scalogram's ability for handling noisy and possibly massive data which show time-shifted patterns. The proposed thresholded scalogram is built on the fast wavelet transform, which can effectively and efficiently capture non-stationary changes in data patterns. Finally, we present a SPC procedure that adaptively determines which wavelet coefficients will be monitored, based on their shift information, which is estimated from process data. By adaptively monitoring the process, we can improve the performance of the control charts for functional data. Using a simulation study, we compare the performance of some of the recommended approaches.

Since semiconductor fabrication processes require numerous steps, cost and yield are critical concerns. In-situ monitoring is therefore vital for process control. However, this goal is currently restricted by the shortage of available sensors capable of performing in this manner. The goal of this research therefore, was to investigate the use of acoustic signals for monitoring and control of semiconductor fabrication equipment and processes. Currently, most methods for process monitoring (such as optical emission or interferometric techniques) rely on "looking" at a process to monitor its status. What was investigated here involved "listening" to the process. Using acoustic methods for process monitoring enhances the amount and sensitivity of data collection to facilitate process diagnostics and control. A silicon acoustic sensor was designed, fabricated, and implemented as a process monitor. Silicon acoustic sensors are favorable because of their utilization of integrated circuit and micromachining processing techniques; thus, enabling miniature devices with precise dimensions, batch fabrication of sensors, good reproducibility, and low costs. The fabricated sensor was used for in-situ monitoring of nickel-iron electrochemical deposition processes. During this process, changes occur in its plating bath as the alloy is being deposited. It is known that changes in the process medium affect the acoustic response. Thus, the sensor was implemented in an electroplating set-up and its response was observed during depositions. By mapping the sensor response received to the film thickness measured at certain times, a predictive model of the plated alloy thickness was derived as a function of sensor output and plating time. Such a model can lead to real-time monitoring of nickel-iron thickness.