A recent International Technology Roadmap for Semiconductors (ITRS) report (2.0, 2015 edition) has shown that Moore’s law is unlikely to hold beyond 2028. There is a need for alternate devices to replace CMOS based devices, if further miniaturization and high energy efficiency is desired. The goal of this dissertation is to experimentally demonstrate the feasibility of nanomagnetic memory and logic devices that can be clocked with acoustic waves in an extremely energy efficient manner. While clocking nanomagnetic logic by stressing the magnetostrictive layer of a multiferroic logic element with with an electric field applied across the piezoelectric layer is known to be an extremely energy-efficient clocking scheme, stressing every nanomagnet separately requires individual contacts to each one of them that would necessitate cumbersome lithography. On the other hand, if all nanomagnets are stressed simultaneously with a global voltage, it will eliminate the need for individual contacts, but such a global clock makes the architecture non-pipelined (the next input bit cannot be written till the previous bit has completely propagated through the chain) and therefore, unacceptably slow and error prone. Use of global acoustic wave, that has in-built granularity, would offer the best of both worlds. As the crest and the trough propagate in space with a velocity, nanomagnets that find themselves at a crest are stressed in tension while those in the trough are compressed. All other magnets are relaxed (no stress). Thus, all magnets are not stressed simultaneously but are clocked in a sequentially manner, even though the clocking agent is global. Finally, the acoustic wave energy is distributed over billions of nanomagnets it clocks, which results in an extremely small energy cost per bit per nanomagnet. In summary, acoustic clocking of nanomagnets can lead to extremely energy efficient nanomagnetic computing devices while also eliminating the need for complex lithography. The dissertation work focuses on the following two topics: Acoustic Waves, generated by IDTs fabricated on a piezoelectric lithium niobate substrate, can be utilized to manipulate the magnetization states in elliptical Co nanomagnets. The magnetization switches from its initial single-domain state to a vortex state after SAW stress cycles propagate through the nanomagnets. The vortex states are stable and the magnetization remains in this state until it is ‘reset’ by an external magnetic field. 2. Acoustic Waves can also be utilized to induce 1800 magnetization switching in dipole coupled elliptical Co nanomagnets. The magnetization switches from its initial single-domain ‘up’ state to a single-domain ‘down’ state after SAW tensile/compressive stress cycles propagate through the nanomagnets. The switched state is stable and non-volatile. These results show the effective implementation of a Boolean NOT gate. Ultimately, the advantage of this technology is that it could also perform higher order information processing (not discussed here) while consuming extremely low power. Finally, while we have demonstrated acoustically clocked nanomagnetic memory and logic schemes with Co nanomagnets, materials with higher magnetostriction (such as FeGa) may ultimately improve the switching reliability of such devices. With this in mind we prepared and studied FeGa films using a ferromagnetic resonance (FMR) technique to extract properties of importance to magnetization dynamics in such materials that could have higher magneto elastic coupling than either Co or Ni.

The resource based radical change from semiconductor manufacturing into the artificial plant factory is studied by understanding the resource capabilities in each industry separately. Due to lack of scientific research in the resource re-utilization process, the phenomenon is explored by studying the role of three different resources from a holistic view. By a qualitative research method, the motivating reasons for the change, the resources involved in the change, duration, and the resource based information were studied. The collected data are analysed under three different categories such as knowledge, infrastructure, and production technology. The identified problems were the unsatisfied resource capabilities, which have to be solved during the change process. As a result of the analysis, a framework is developed by combining all the three resources from a holistic view, in the change process. The framework is structured in three separate phases and inferred to support the resource re-utilization in the radical change process.

In 1960's Gordon Moore predicted that the increase in the number of components in integrated circuits would exponentially decrease the relative manufacturing cost per component with time. The semiconductor industry has managed to keep that pace for nearly 45 years and one of the main contributors to this phenomenal improvement in technology is advancement in the field of lithography. However, the technical challenges ahead are severe and the future roadmap laid by the International Technology Roadmap for Semiconductors looks mostly red (i.e. no solution has been found to specific problem). There are efforts in the industry and academia directed toward development of newer, alternative lithographic techniques. Step and Flash Imprint Lithography (SFIL) has recently emerged as one of the most promising alternatives, capable of producing high resolution patterns. While it has numerous advantages over conventional photolithography, several engineering challenges must be overcome to eliminate defects due to the nature of contact imprinting if SFIL is to be a viable alternative technique for manufacturing tomorrow's integrated circuits. The complete filling of template features is vital in order for the SFIL imprint process to truly replicate the template features. The feature filling phenomena for SFIL was analyzed by studying diffusion of a gas, entrapped in the features, through liquid imprint resist. A simulation of the dynamics of feature filling for different pattern configurations and process conditions during the SFIL imprint step is presented. Simulations show that initial filling is pressure-controlled and very rapid; while the rest of the feature filling is diffusion-controlled, but fast enough that diffusion of entrapped gas is not a cause for non-filling of features. A theory describing pinning of an air-liquid interface at the feature edge of a template during the SFIL imprint step was developed, which shows that pinning is the main cause of non-filling of features. Pinning occurs when the pressure at the air-liquid interface reaches the pressure of the bulk liquid. At this condition, there is no pressure gradient or driving force to move the liquid and fill the feature. The effect of several parameters on pinning was examined. A SFIL process window was established and template modifications are proposed that minimize the pinning at the feature edge while still preventing any extrusion along the mesa (pattern containing area on the template) edge. Part of semiconductor manufacturing community believes that optical lithography has the capability to drive this industry further and is committed to the continuous improvement of current optical patterning approaches. Some of the major challenges with shrinking critical dimensions (CDs) in coming years are the control of line-edge roughness (LER) and other related defects. The current CDs are such that the presence or absence of even a single polymer molecule can have a considerable impact on LER. Therefore molecular level understanding of each step in the patterning process is required. Computer simulations are a cost-effective approach to explore the huge process space. Mesoscale modeling is one promising approach to simulations because it captures the stochastic phenomena at a molecular level within reasonable computational time. The modeling and simulation of the post-exposure bake (PEB) and the photoresist dissolution steps are presented. The new simulator enables efficient exploration of the statistical excursions that lead to LER and the formation of insoluble residues during the dissolution process. The relative contributions of the PEB and the dissolution step to the LER have also been examined in the low/high frequency domain. The simulations were also used to assess the commonly proposed measures to reduce LER. The goal of the work was to achieve quantification of the effect of changes in resist composition, developer concentration, and process variables on LER and the associated defectivity. / text

The goal of the study presented in this thesis was the improvement of estimation and monitoring procedures for condition monitoring of belt tension and misalignment in belt-driven automated material handling systems widely used in modern semiconductor manufacturing systems. In pursuit of this goal, two 3-factor, 3-level experiments were designed to study how belt vibration characteristics depend on changes in belt length, belt tension, belt misalignment, and initial location of the excitation of belt vibration. Dependent variables in each of the experiments were drawn from a denoised frequency spectrum calculated from an Autoregressive model of the belt vibration time-series. A feature vector was developed from the Autoregressive features via variance based sensitivity analysis. Results showed that belt vibration characteristics were sensitive to changes in all of the independent variables examined. These results motivated the design of a device to improve the standardized technique widely used to monitor belt tension in belt-driven material handling systems. Reducing variance in the belt length and the location of the initial excitation of belt vibration yielded a reduction of tension estimate standard deviation an order of magnitude, as compared to a human performing the standardized technique. Thus, the use of this device provided higher belt tension estimate resolution. Future work that could lead to a less intrusive technique is presented. / text

In the recent years threaded run-to-run (RtR) control algorithms have experienced drawbacks under certain circumstances, one such trait is when applied to high-mix of products such as in Application Specific Integrated Circuits (ASIC) foundries. The variations in the process are a function of the product being manufactured as well as the tool being used. The presence of semiconductor layers increases the number of times the lithography process must be repeated. Successive layers having different patterns must be exposed using different reticles/masks in order to maximize tool utilizations. The objectives of this research are to develop a set of methodologies for evaluation and extension of threaded control applied to overlay. This project defines methods to quantify the efficacy of threaded controls, finds the drawbacks of threaded control under production of high mix of semiconductors and suggests extensions and alternatives to improve threaded control. To evaluate the performance of threaded control, extensive simulations were performed in MATLAB. The effects of noise, disturbances, sampling and delays on the control and estimation performance of threaded controller were studied through these simulations. Based on the results obtained, several ideas to extend threaded control by reducing overall number of threads, by improving thread definitions and combination have been introduced. A unique idea of sampling the measurements dynamically based on the estimation accuracy is also presented. Future work includes implementing the extensions to threaded control suggested in this work in real production data and comparing the results without the use of those methods. Future work also includes building new alternatives to threaded control. / text

This dissertation presents a series of studies related to the characterization and optimization of consumables during Chemical Mechanical Planarization (CMP). These studies are also evaluated with the purpose of reducing the cost of ownership as well as minimizing the potential environmental impacts. It is well known that pad-wafer contact and pad surface micro-structure have significant impacts on polishing performance. The first study in this dissertation investigates the effect of pad surface contact and topography on polishing performance during copper CMP. Two different types of diamond discs (3M A2810 disc and MMC TRD disc) are used to condition the polishing pad. Pad surface contact area and topography are analyzed using laser confocal microscopy and scanning electron microscopy (SEM) to illustrate how variations in pad surface micro-texture affect the copper removal rate and the coefficient of friction (COF). Polishing results show that the 3M A2810 disc generates significantly higher COF (16%) and removal rate (39%) than the MMC TRD disc. Pad surface analysis results show that the 3M A2810 disc and MMC TRD disc generate similar pad surface height probability density function and pad surface abruptness. On the other hand, the MMC TRD disc generates large flat near contact areas that correspond to fractured and collapsed pore walls while the 3M A2810 disc generates solid contact area and clear pore structures. The fractured and collapsed pore walls generated by the MMC TRD disc partly cover the adjacent pores, making the pad surface more lubricated during wafer polishing and resulting in a significantly lower COF and removal rate. In the next study, the individual "large" pad surface contact areas are differentiated from the "small" contact areas and their role in copper CMP is investigated. Surface topography and the structure of a typical individual large contact area are examined via laser confocal microscopy and SEM. In addition, the Young's Modulus of the pad surface material is simulated. A case study is presented to illustrate the role of the individual large contact area of IC1000 K-groove pad in copper CMP. SEM analysis shows that the individual large pad surface contact areas are induced by fractured pore walls and loosely attached pad debris. Simulation results indicate that individual large contact areas correspond to very low values of the Young's modulus (about 50 MPa). Such low values indicate that the pad material is soft and the summit underlying the individual large contact is not fully supported. As a result, individual large contact area implies low contact pressure and may contribute little to removal rate. Case study results confirm that the individual large contact area has minimal contribution to removal rate and indicate that the removal rate is mainly caused by small individual contact areas. In our case, small contact areas correspond to those smaller than 9 square microns. We believe that this methodology can be also applied for other kinds of pad, although the threshold values that may define "small" and "large" individual contact areas for different pads and processes need to be further investigated. In the third study, the effect of pad surface micro-texture in interlayer dielectric CMP is also investigated. Blanket 200-mm oxide wafers are polished and the polishing pad is conditioned under two different conditioning forces (26.7 and 44.5 N). Results show that when conditioning force is increased from 26.7 to 44.5 N, oxide removal rate increases by 65% while COF increases by only 7%. Pad surface contact area and topography are measured and analyzed to illustrate their effects on the oxide removal rate. While the two conditioning forces generate similar pad surface abruptness, pad surface contact area is significantly lower (by 71%) at the conditioning force of 44.5 N. Such dramatic decrease in pad surface contact area leads to a significant increase in local contact pressure and therefore results in a significant increase in oxide removal rate. The oxide removal rate and local contact pressure exhibits a Prestonian relationship. Besides the above studies on the effect of the pad surface micro-texture during blanket wafer polishing, the fourth study investigates how pad micro-texture affects dishing and erosion during shallow trench isolation (STI) patterned wafer polishing. Two different types of diamond discs (3M A2810 disc and MMC TRD disc) are used to condition the pad during wafer polishing. Dishing and erosion analysis for the patterned wafer polishing is performed using a surface profiler. To illustrate the effect of pad surface micro-texture on dishing and erosion, pad surface abruptness and mean pad summit curvature are analyzed using laser confocal microscopy. Polishing results show that the two discs generate similar blanket wafer removal rates, while the MMC TRD disc generate significantly higher dishing and erosion than the 3M A2810 disc during patterned wafer polishing. Results of pad surface micro-texture analysis show that the MMC TRD disc generates sharper asperities with higher mean pad summit curvature than the 3M A2810 disc, resulting in higher dishing and erosion. Another contribution of this dissertation is the development of a slurry film thickness quantification technique using ultraviolet-enhanced fluorescence. The technique is developed to measure slurry film thickness at any location of interest. In the next study of this dissertation, this new technique is applied to determine how two different slurry application/injection schemes (standard pad center area application method and novel slurry injection system) along with various polishing conditions such as sliding velocity, ring pressure and slurry flow rate affect slurry availability in the bow wave region of the polisher. For the standard pad center area application method, slurry is directly applied onto the pad center area and a large amount of fresh slurry flow directly off the pad surface without flowing to the pad-retaining ring interface due to the centrifugal forces. For the novel slurry injection system, slurry is introduced through an injector that is placed adjacent (<3 cm) to the retaining ring on the pad surface. Such a close distance between the injector and retaining ring allows most of the fresh slurry to be delivered efficiently to the leading edge of the retaining ring after it is injected onto the pad surface. Results show that the novel slurry injection system generates consistently thicker bow waves (up to 104 percent) at different sliding velocities, slurry flow rates and ring pressures, therefore providing more slurry availability for the pad-retaining ring interface and potentials for slurry consumption reduction in CMP processes. First order calculations yield estimates of slurry savings associated with the novel slurry injection system ranging between 8 and 48 percent depending on specific process conditions. In the last study of this dissertation, the effect of retaining ring slot design and polishing conditions on slurry flow dynamics at the bow wave is investigated. The ultraviolet-enhanced fluorescence technique is employed to measure the slurry film thickness at the bow wave for two retaining rings with different slot designs. Multiple sliding velocities, slurry flow rates and ring pressures are investigated. Results show that the retaining ring with the sharp angle slot design (PEEK-1) generates significantly thicker (on average 48%) slurry films at the bow wave than PEEK-2 which has a rounded angle slot design. For PEEK-1, film thickness at the bow wave increases with the increasing of flow rate and ring pressure and decreases with the increasing of sliding velocity. On the other hand, film thickness at bow wave does not change significantly for the PEEK-2 ring at different polishing conditions indicating an apparent robustness of the PEEK-2 design to various operating conditions. With retaining rings having different designs, and all else being the same, a thinner bow wave is preferred since it is indicative of a ring design that allows more slurry to flow into the pad-wafer interface. Therefore, the work underscores the importance of optimizing retaining ring slot design and polishing conditions for efficient slurry utilization.

The evolution of the MOSFET technology has been driven by the aggressive shrinkage of the device size to improve the device performance and to increase the circuit density. Currently, many research demonstrated that the continuous polycrystalline silicon film in the floating-gate dielectric could be replaced with nanocrystal (nc) embedded high-k thin film to minimize the charge loss due to the defective thin tunnel dielectric layer. This research deals with both the statistical aspect of reliability and electrical aspect of reliability characterization as well. In this study, the Zr-doped HfO2 (ZrHfO) high-k MOS capacitors, which separately contain the nanocrystalline zinc oxide (nc-ZnO), silicon (nc-Si), Indium Tin Oxide (nc-ITO) and ruthenium (nc-Ru) are studied on their memory properties, charge transportation mechanism, ramp-relax test, accelerated life tests, failure rate estimation and thermal effect on the above reliability properties. C-V hysteresis result show that the amount of charges trapped in nanocrystal embedded films is in the order of nc-ZnO>nc-Ru>nc-Si~nc-ITO, which might probably be influenced by the EOT of each sample. In addition, all the results show that the nc-ZnO embedded ZrHfO non-volatile memory capacitor has the best memory property and reliability. In this study, the optimal burn-in time for this kind of device has been also investigated with nonparametric Bayesian analysis. The results show the optimal burn-in period for nc-ZnO embedded high-k device is 5470s with the maximum one-year mission reliability.

As the world faces an energy crisis with depleting fossil fuel reserves, alternate energy sources are being researched ever more seriously. In addition to renewable energy sources, energy recycling and energy scavenging technologies are also gaining importance. Technologies are being developed to scavenge energy from ambient sources such as vibration, radio frequency and low grade waste heat, etc. Waste heat is the most common form of wasted energy and is the greatest potential source of energy scavenging. Pyroelectricity is the property of some materials to change the surface charge distribution with the change in temperature. These materials produce current as temperature varies in them and can be utilized to convert thermal energy to electrical energy. In this work a novel approach to vary temperature in pyroelectric material to convert energy has been investigated. Microelectromechanical Systems or MEMS is the new technology trend that takes advantage of unique physical properties at micro scale to create mechanical systems with electrical interface using available microelectronic fabrication techniques. MEMS can accomplish functionalities that are otherwise impossible or inefficient with macroscale technologies. The energy harvesting device modeled and developed for this work takes full benefit of MEMS technology to cycle temperature in an embedded pyroelectric material to convert thermal energy from low grade waste heat to electrical energy. Use of MEMS enables improved performance and efficiency and overcomes problems plaguing previous attempts at pyroelectric energy conversion. A Numerical model provides accurate prediction of MEMS performance and sets design criteria, while physics based analytical model simplifies design steps. A SPICE model of the MEMS device incorporates electrical conversion and enables electrical interfacing for current extraction and energy storage. Experimental results provide practical implementation steps towards of the modeled device. Under ideal condition the proposed device promises to generate energy density of 400 W/L.

abstract: Economic and environmental concerns necessitate the preference for retrofits over new construction in manufacturing facilities for incorporating modern technology, expanding production, becoming more energy-efficient and improving operational efficiency. Despite the technical and functional challenges in retrofits, the expectation from the project team is to; reduce costs, ensure the time to market and maintain a high standard for quality and safety. Thus, the construction supply chain faces increasing pressure to improve performance by ensuring better labor productivity, among other factors, for efficiency gain. Building Information Modeling (BIM) & off-site prefabrication are determined as effective management & production methods to meet these goals. However, there are limited studies assessing their impact on labor productivity within the constraints of a retrofit environment. This study fills the gap by exploring the impact of BIM on labor productivity (metric) in retrofits (context). BIM use for process tool installation at a semiconductor manufacturing facility serves as an ideal environment for practical observations. Direct site observations indicate a positive correlation between disruptions in the workflow attributed to an immature use of BIM, waste due to rework and high non-value added time at the labor work face. Root-cause analysis traces the origins of the said disruptions to decision-factors that are critical for the planning, management and implementation of BIM. Analysis shows that stakeholders involved in decision-making during BIM planning, management and implementation identify BIM-value based on their immediate utility for BIM-use instead of the utility for the customers of the process. This differing value-system manifests in the form of unreliable and inaccurate information at the labor work face. Grounding the analysis in theory and observations, the author hypothesizes that stakeholders of a construction project value BIM and BIM-aspects (i.e. geometrical information, descriptive information and workflows) differently and the accuracy of geometrical information is critical for improving labor productivity when using prefabrication in retrofit construction. In conclusion, this research presents a BIM-value framework, associating stakeholders with their relative value for BIM, the decision-factors for the planning, management and implementation of BIM and the potential impact of those decisions on labor productivity. / Dissertation/Thesis / Doctoral Dissertation Construction 2015

abstract: Semiconductor manufacturing is one of the most complex manufacturing systems in today’s times. Since semiconductor industry is extremely consumer driven, market demands within this industry change rapidly. It is therefore very crucial for these industries to be able to predict cycle time very accurately in order to quote accurate delivery dates. Discrete Event Simulation (DES) models are often used to model these complex manufacturing systems in order to generate estimates of the cycle time distribution. However, building models and executing them consumes sufficient time and resources. The objective of this research is to determine the influence of input parameters on the cycle time distribution of a semiconductor or high volume electronics manufacturing system. This will help the decision makers to implement system changes to improve the predictability of their cycle time distribution without having to run simulation models. In order to understand how input parameters impact the cycle time, Design of Experiments (DOE) is performed. The response variables considered are the attributes of cycle time distribution which include the four moments and percentiles. The input to this DOE is the output from the simulation runs. Main effects, two-way and three-way interactions for these input variables are analyzed. The implications of these results to real world scenarios are explained which would help manufactures understand the effects of the interactions between the input factors on the estimates of cycle time distribution. The shape of the cycle time distributions is different for different types of systems. Also, DES requires substantial resources and time to run. In an effort to generalize the results obtained in semiconductor manufacturing analysis, a non- complex system is considered. / Dissertation/Thesis / Masters Thesis Mechanical Engineering 2017