Title of dissertation: GROWTH OF Zn POLAR BeMgZnO/ZnO HETEROSTRUCTURE WITH TWO DIMENSIONAL ELECTRON GAS (2DEG) AND FABRICATION OF SILVER SCHOTTKY DIODE ON BeMgZnO/ZnO HETEROSTRUCTURE By Md Barkat Ullah, Ph.D A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering at Virginia Commonwealth University. Virginia Commonwealth University,2017 Major Director: Dr. Hadis Morkoç, Professor, Electrical and Computer Engineering This thesis focuses on growth of Zn polar BeMgZnO/ZnO heterostructure on GaN/sapphire template with two dimensional electron gas (2DEG) for the application of UV photodetector/emitter and high speed electronics. The motivation of using BeMgZnO as a barrier layer originates from the need to reach plasmon-LO phonon resonance in order to obtain minimum longitudinal optical (LO) phonon lifetime. Presence of 2DEG was realized in BeMgZnO/ZnO heterostructure only when the Zn polarity was achieved during the nucleation growth of ZnO on GaN/sapphire template. It was found that, polarity of ZnO on (0001) GaN/sapphire template can be controlled by the oxygen to Zn ratio used during the nucleation growth. To obtain high structural and optical quality of BeMgZnO quaternary alloy, growth kinetics of BeMgZnO layer has been studied at the temperature range from 450°C-500°C. We have achieved the growth of single crystal Be.03Mg00.15ZnO alloy at 500 °C, more than 100°C higher compared to what reported in literature, on the (0001) GaN/sapphire template through the control of Zn/(Be+Mg) flux ratio. We have also observed a thermodynamic limitation of Mg incorporation into the wurtzite BeMgZnO alloy where the excess Mg adatom accumulated in the growing surface as a MgO rich cluster. Two dimensional electron gas with high (1.2×1013cm-2) sheet carrier density was achieved at the Be0.03Mg0.41ZnO/ZnO interface through strain engineering by incorporating Be into MgZnO ternary alloy. To obtain the similar sheet carrier density it would require above 60% of Mg in MgZnO/ZnO heterostructure with reduced structural quality. A systematic comparison of sheet carrier density has been made with the already reported results from Zn polar MgZnO/ZnO heterostructure as well as with the theoretical calculation. Silver Schottky diode on Be0.02Mg0.26ZnO/ZnO heterostructure with barrier height 1.07 eV and ideality factor 1.22 was obtained with 8 order of rectification ratio. The temperature-dependent electrical characteristics were studied by using temperature dependent current-voltage (I-V) measurements. Richardson constant value of 34.8 Acm-2K-2 was found experimentally which was close to the theoretical value of 36 Acm-2K-2 known for Be0.02Mg0.26ZnO alloy.

The outstanding electrical and material properties of Graphene have made it a promising material for several fields of analog applications, though its zero bandgap precludes its application in digital and logic devices. With its remarkably high electron mobility at room temperature, Graphene also has strong potential for terahertz (THz) plasmonic devices. However there still are challenges to be solved to realize Graphene’s full potential for practical applications. In this dissertation, we investigate solutions for some of these challenges. First, to reduce the access resistances which significantly reduces the radio frequency (RF) performance of Graphene field effect transistors (GFETs), a novel device structure consisting of two additional contacts at the access region has been successfully modeled, designed, microfabicated/integrated, and characterized. The additional contacts of the proposed device are capacitively coupled to the device channel and independently biased, that induce more carriers and effectively reduce access resistance. In addition to that, in this dissertation, bandgap has been experimentally introduced to semi-metallic Graphene, by decorating with randomly distributed gold nano-particles and zinc oxide (ZnO) nano-seeds, where their interaction breaks its sublattice symmetry and opens up bandgap. The engineered bandgap was extracted from its temperature dependent conductivity characteristics and compared with reported theoretical estimation. The proposed method of device engineering combined with material bandgap engineering, on a single device, introduces a gateway towards high speed Graphene logic devices. Finally, THz plasmon generation and propagation in Graphene grating gate field effect transistors and Graphene plasmonic ring resonators have been investigated analytically and numerically to explore their potential use for compact, solid state tunable THz detectors.

In this research, Ni–NiOx–Cr and Ni–NiOx–ZnO–Cr metal-insulator-metal (MIM) junction based tunnel diodes have been investigated for the purpose of a wide-band detector. An MIM diode has a multitude of applications such as harmonic mixers, rectifiers, millimeter wave and infrared detectors. Femtosecond-fast electron transport in MIM tunnel diodes also makes them attractive for energy-harvesting devices. These applications require the tunnel diodes to have high current-asymmetry and non-linear current-voltage behavior at low applied voltages and high frequencies. Asymmetric and non-linear characteristics of Ni–NiOx-Cr MIM tunnel diodes were enhanced in this research by the addition of ZnO as a second insulator layer in the MIM junction to form metal-insulator-insulator-metal (MIIM) structure. Electrical characteristics were studied in a voltage range of for the single-insulator Ni–NiOx–Cr and double-insulator Ni–NiOx–ZnO–Cr tunnel diodes. Since the electrical characteristics of the diode are sensitive to material selection, material arrangement, thickness, deposition techniques and conditions, understanding the diode behavior with respect to these factors is crucial to developing a robust diode structure. Thus, ZnO insulator layer in MIIM junction was deposited by two different techniques: sputtering and atomic layer deposition (ALD). Also, the optical properties were characterized for the sputter deposited NiOx insulator layers by ellipsometry and the impact of annealing was explored for the NiOx optical properties. The Ni–NiOx–Cr MIM tunnel diodes provide low resistance but exhibit a low (~1) current-asymmetry. Asymmetry increased by an order of magnitude in case of Ni–NiOx–ZnO–Cr MIIM tunnel diode. The sensitivity of the MIM and MIIM diodes was 11 V-1 and 16 V-1, respectively. The results suggest that the MIIM diode can provide improved asymmetry at low voltages. The tunneling behavior of the device was also demonstrated in the 4-298K temperature range. It is hypothesized that the improved performance of the bilayer insulator diode is due to resonant tunneling enabled by the second insulator. Finally, the MIM and MIIM devices were investigated for wide-band detection up to 50GHz (RF) and 0.3THz (optical).

La prise en compte de machines à traitement par batch dans les problèmes d’ordonnancement d’ateliers complexes de type job-shop est particulièrement difficile. La fabrication de semiconducteurs est probablement l’une des applications pratiques les plus importantes pour ce types de problèmes. Nous considérons un problème d’ordonnancement de type job-shop flexible avec « p-batching », des flux rentrants, des temps de préparation dépendant de la séquence et des dates de début au plus tôt. Le but c’est d’optimiser différentes fonctions objectives régulières.Les approches existantes par graphe disjonctif pour ce problème utilise des nœuds dédiés pour représenter explicitement les batches. Afin de faciliter la modification du graphe conjonctif, notre nouvelle modélisation réduit cette complexité en modélisant les décisions de batching à travers les poids des arcs. Une importante contribution de cette thèse est un algorithme original qui prend les décisions de batching lors du parcours du graphe. Cet algorithme est complété par un déplacement (« move ») intégré qui permet de reséquencer ou réaffecter les opérations. Cette combinaison donne un voisinage riche que nous appliquons dans une approche méta-heuristique de type GRASP.Nous étendons cette approche en prenant en compte de nouvelles contraintes qui ont un rôle important dans l’application industrielle considérée. En particulier, nous modélisons de manière explicite les ressources internes des machines, et nous considérons un temps maximum d’attente entre deux opérations quelconques d’une gamme de fabrication. Les résultats numériques sur des instances de la littérature pour des problèmes plus simples ainsi que sur de nouvelles instances montrent la généricité et l’applicabilité de notre approche. Notre nouvelle modélisation permet de faciliter les extensions à d’autres contraintes complexes rencontrées dans les applications industrielles. / The integration of batching machines within a job-shop environment leads to a complex job-shop scheduling problem. Semiconductor manufacturing presumably represents one of the most prominent practical applications for such problems. We consider a flexible job-shop scheduling problem with p-batching, reentrant flows, sequence dependent setup times and release dates while considering different regular objective functions. The scheduling of parallel batching machines and variants of the job-shop scheduling problem are well-studied problems whereas their combination is rarely considered.Existing disjunctive graph approaches for this combined problem rely on dedicated nodes to explicitly represent batches. To facilitate modifications of the graph, our new modeling reduces this complexity by encoding batching decisions into edge weights. An important contribution is an original algorithm that takes batching decisions “on the fly” during graph traversals. This algorithm is complemented by an integrated move to resequence and reassign operations. This combination yields a rich neighborhood that we apply within a GRASP based metaheuristic approach.We extend this approach by taking further constraints into account that are important in the considered industrial application. In particular, we model internal resources of machines in detail and take maximum time lag constraints into account. Numerical results for benchmark instances of different problem types show the generality and applicability of our approach. The conciseness of our idea facilitates extensions towards further complex constraints needed in real-world applications.

This dissertation focuses on the chemistry, detection, and control of metals and metal contaminants during manufacturing of integrated circuits (ICs) on silicon wafers. Chapter 1 begins with an overview of IC manufacturing, including discussion of the common aqueous cleaning solutions, metallization processes, and analytical techniques that will be investigated in subsequent chapters. Chapter 2 covers initial investigations into the chemistry of the SC2 clean - a mixture of HCl, H2O2, and DI water - especially on the behavior of H2O2 in this solution and the impact of HCl concentration on metal removal from particle addition to silicon oxide surfaces. Chapter 3 includes a more generalized investigation of the chemistry of metal ions in solution and how they react with the silicon oxide surfaces they are brought into contact with, concluding with illumination of the fundamental chemical principles that govern their behavior. Chapter 4 shows how metal contaminants behave on silicon wafers when subjected to the high temperature (≥ 800 °C) thermal cycles that are encountered in IC manufacturing. It demonstrates that knowledge of some fundamental thermodynamic properties of the metals allow accurate prediction of what will happen to a metal during these processes. Chapter 5 covers a very different but related aspect of metal contamination control, which is the effectiveness of metal diffusion barriers (e.g. Ru) in holding a metal of interest, (e.g. Cu), where it is wanted while preventing it from migrating to places where it is not wanted on the silicon wafer. Chapter 6 concludes with an overview of the general chemical principles that have been found to govern the behavior of metals during IC manufacturing processes.

Built with nanomagnets, a spintronic device called the all-spin logic (ASL) device carries information with only spin currents, resulting in a low power supply--10 mV. This voltage is 100 times smaller than the conventional CMOS devices (usually 0.8~1V). The potential for improved energy efficiency made possible by the low operating voltage of ASL makes it one of the most promising devices among its post-CMOS competitors. The basic working principles of ASL device are introduced in this thesis and two complementary approaches to studying energy efficiency of computation are applied to a common set of ASL circuits: (1) a circuit simulation approach that provides efficiency estimates for specific ASL circuit realizations, and (2) a physical-information-theoretic approach that reveals fundamental efficiency bounds for ASL circuits as limited by irreversible information loss. The results of this study support the expectation that the energy efficiency of computation in ASL can far exceed that of CMOS. However, it also reveals that ASL efficiencies--shown to exceed fundamental limits by many orders of magnitude in the ASL implementations studied here--are unlikely to approach fundamental limits because of the unavoidable energetic overhead cost of maintaining spin currents.

Despite the fact that discrete event simulation has existed for more than 50 years, sufficiently large simulation models covering several enterprises are still not known. Those simulation models that do exist in the industry are usually used to test individual scenarios rather than for optimization. The main reason for this is the high computational complexity. A solution could be the use of simplified models. However, this problem has not been sufficiently investigated. This dissertation is devoted to the problem. The problem can be briefly formulated as the following question: How to simplify a simulation model in order to minimize the run time of the simplified model and maximize its accuracy? Unfortunately, the answer to this question is not simple and requires many problems to be solved. This thesis formulates these problems and proposes ways to solve them. Let us briefly list them. In order to simplify simulation models in conditions close to real ones, it is suggested to use statistical models specially developed for this purpose. Based on experimental data, this thesis analyzes various ways of aggregating process flows. However, the main method of simplification is the substitution of tool sets for delays. Two approaches to the use of delays are considered: distributed and aggregated delays. Obviously, the second approach reduces the simulation time for the simplified model more. However, distributed delays allow us to identify meaningful effects arising from the simulation model simplification. Moreover, it is interesting to compare the two methods. A significant problem is determining the criterion for selecting the tool set to be substituted. In this thesis, ten heuristics are considered for this purpose, each with two variations. Another problem is the calculation of delays. Here we consider three variations and compare them in terms of the accuracy of simplified simulation models. In this thesis, we consider two dispatching rules: First In First Out and Critical Ratio. The first rule provides a more predictable behavior of simplified simulation models and makes it easier to understand the various effects that arise. The second rule allows us to test the applicability of the proposed simplification methods to conditions close to the real world. An important problem is the analysis of the obtained results. Despite the fact that this issue is well studied in the field of simulation, it has its own nuances in the case of analyzing the simplified models' accuracy. Moreover, in the scientific literature, various recommendations were found, which were experimentally tested in this thesis. As a result, it turned out that not all traditional accuracy measurements can be adequately used for the analysis of simplified models. Moreover, it is additionally worth using those techniques and methods, which usually in simulation modeling refer to the analysis of input data. In this thesis, about 500,000 experiments were performed, and more than 2,000 reports were generated. Most of the figures presented in this thesis are based on specific reports of the most significant interest.:1 Introduction 6 1.1 Preamble 7 1.2 Scope of the research 8 1.3 Problem definition 10 2 State of the art 12 2.1 Research object 13 2.1.1 Tool sets 15 2.1.2 Down and PM events 17 2.1.3 Process flows 18 2.1.4 Products 20 2.2 Simplification 21 2.2.1 Simplification approaches 23 2.2.2 Tool set and process step simplification 24 2.2.3 Process flow and product nomenclature simplification 26 2.2.4 Product volume and lot release rule simplification 27 2.3 Discussion about bottleneck 29 2.3.1 Bottleneck definitions 29 2.3.2 Why do we consider bottlenecks? 32 2.3.3 Bottleneck detection methods 33 3 Solution 41 3.1 Design of experiments 42 3.1.1 α – forecast scenario 43 3.1.2 β – lot release strategy 60 3.1.3 γ – process flow aggregation 64 3.1.4 δ – delay position 78 3.1.5 ε – dispatching rule 79 3.1.6 ζ – sieve functions 80 3.1.7 η – delay type 89 3.1.8 Experimental environment 90 3.2 Experiment analysis tools 93 3.2.1 Errors 93 3.2.2 Deltas 94 3.2.3 Correlation coefficients and autocorrelation function 96 3.2.4 T-test, U-test, and F-test 97 3.2.5 Accuracy measurements based on the probability density function 98 3.2.6 Accuracy measurements based on the cumulative distribution function 99 3.2.7 Simple example 100 3.2.8 Simulation reports 104 3.2.9 Process step reports 105 3.2.10 Model runtime characteristics 106 4 Evaluation 111 4.1 Scenario “Present”, static product mix and all process flows (α1, β1, γ1) 113 4.1.1 Similarity and difference of errors and deltas for static product mix (β1) 113 4.1.2 “Butterfly effect” of Mean Absolute Error (MAE) 114 4.1.3 “Strange” behavior of correlation and autocorrelation 116 4.1.4 “Pathological” behavior of Mean Absolute Error (MAE) 117 4.1.5 Lot cycle time average shift 120 4.1.6 Delay type (η) usage analysis 125 4.1.7 Introduction to sieve function (ζ) analysis 132 4.1.8 Delay position (δ) analysis 136 4.1.9 δ2 calibration (improvement of the lot cycle time average shift) 140 4.1.10 Using t-test, U-test, and F-test as accuracy measurements 144 4.1.11 Using accuracy measurements based on the probability density function 153 4.1.12 Using accuracy measurements based on the cumulative distribution function 159 4.1.13 X-axes of the accuracy measurements 163 4.1.14 Sieve function (ζ) comparison (accuracy comparison) 165 4.2 Scenario “Present”, dynamic product mix and all process flows (α1, β2, γ1) 174 4.2.1 Modeling time gain, autocorrelation, correlation, and MAE in β2 case 174 4.2.2 Errors and deltas in β2 case 176 4.2.3 Lot cycle time average shift in β2 case 177 4.2.4 Accuracy measurement in β2 case and accuracy comparison 180 4.3 Scenario “Past + Future”, dynamic product mix and all process flows (α2, β2, γ1) 187 4.3.1 Delays in α2 case 187 4.3.2 Deltas, correlation, and MAE in α2 case 190 4.3.3 Accuracy comparison 192 4.4 Process flow aggregation (α1, β1, γ1) vs. (α1, β1, γ2) vs. (α1, β1, γ3) 196 4.4.1 Lot cycle time average 196 4.4.2 Lot cycle time standard deviation 200 4.4.3 Correlation, Mean Absolute Error, and Hamming distance 202 4.4.4 Accuracy comparison 204 4.5 Additional experiments of gradual process step merge (α1, β1, γ3). 210 4.5.1 Gradual merge experimental results. 210 4.5.2 Theoretical explanation of the gradual merge experimental results 212 4.6 Process flow aggregation (α1, β2, γ1) vs. (α1, β2, γ2) vs. (α1, β2, γ3) 214 4.6.1 Correlation, MAE, and deltas 214 4.6.2 Accuracy comparison 218 4.7 Process flow aggregation (α2, β2, γ1) vs. (α2, β2, γ2) vs. (α2, β2, γ3) 223 4.7.1 Delays in {α2, γ2} case 223 4.7.2 Accuracy comparison 226 5 Conclusions and outlook 228 6 Appendices. 232 6.1 Appendix A. Simulation reports overview. 232 6.2 Appendix B. Sieve functions comparison for {α1, β1, γ1, δ2_cal, ε1} 237 7 References 245

Flexible Hybrid Electronics (FHEs) offer many advantages to the future of wearable technology. By combining the dynamic performance of conductive inks, and the functionality of ultra-thinned, traditional IC technology, new FHE devices allow for development of applications previously excluded by relying on a specific type of electronics technology. The characterization and reliability analysis of stretchable conductive inks paired with ultra-thin silicon die in theµm range was conducted. A silver based ink designed to be stretchable was screen printed on a TPU substrate and cured using box oven, conveyor convection oven, and photonic curing processes. Reliability tests were conducted including a tape test, crease test, wash test, and abrasion test. Optimization of each curing process resulted in all three methods’ ability to achieve the ink sheet resistance specification of <75mΩ/square/25µm. Reliability tests on the printing concluded that, if fully cured, all samples achieve similar reliability performance. Additionally, a series of 10 mm x 10 mm ultra-thin die were characterized using stylus profilometry and optical measurement in order to test the die quality and readiness for assembly. The die had been thinned from an initial thickness down of 600 µm to a target of 50 µm. A direct inverse relationship was shown between die thickness and die warpage, likely due to high levels of internal stress caused by the dicing and thinning process. Finally, an innovate pairing of serpentine copper clad traces on TPU was tested for reliability performance using traditional solder for die attachment.

Graphene electronics represent a developing field where many material properties and devices characteristics are still unknown. Researching several possible fabrication processes creates a fabrication process using resources found at Cal Poly a local industry sponsor. The project attempts to produce a graphene network in the shape of a fractal Sierpinski carpet. The fractal geometry proves that PDMS microfluidic channels produce the fine feature dimensions desired during graphene oxide deposit. Thermal reduction then reduces the graphene oxide into a purified state of graphene. Issues arise during thermal reduction because of excessive oxygen content in the furnace. The excess oxygen results in devices burning and additional oxidation of the gate contacts that prevents good electrical contact to the gates. Zero bias testing shows that the graphene oxide resistance decreases after thermal reduction, proving that thermal reduction of the devices occurs. Testing confirms a fabrication process producing graphene electronics; however, revision of processing steps, especially thermal reduction, should greatly improve the yield and functionality of the devices.

Vernier Tuned Distributed Bragg Reflector (VT-DBR) lasers have had great success in the field of Swept-Source Optical Coherence Tomography (SS-OCT) due to their continuous and nearly 40 nm wavelength tuning range in a single longitudinal mode. Fast sweeps allow for real time imaging with micrometer resolution at a distance of a few centimeters. While this laser has proven quite useful as a medical imaging tool via OCT, it has yet to similarly prove itself for general light detection and ranging (LIDAR) applications due to range limitations that arise from a finite laser coherence length. The goal of this thesis is to explore LIDAR applications for VT-DBR lasers and how to improve VT-DBR performance for LIDAR. In the scope of this work, LIDAR is laser imaging at tens or hundreds of meters with a resolution finer than 10cm. In order to achieve this kind of LIDAR performance with a VT-DBR laser, the laser must have a linewidth less than 1MHz over a tuning range of around 10GHz. This thesis outlines two methods towards this goal. The bulk of this work is dedicated to looking for and characterizing VT-DBR tuning paths with fundamentally narrow linewidth using microampere currents in both forward and reverse bias conditions. The second part of this thesis is a preliminary design of an optical frequency-locked loop to reduce laser phase noise, which subsequently reduces the laser linewidth. By tuning with small currents in the forward bias condition, nearly the entire range of laser wavelengths could be tuned to, but areas of narrow linewidth were both sparse and very sensitive to any change in bias. The reverse bias case showed limited but continuous tuning with increased reverse current magnitude. In this reverse biased photo-detector mode the laser exhibited narrower linewidth less than 15MHz, with the linewidth at intrinsically narrow levels when all three sections reverse biased. Also promising was a subset of reverse bias conditions that only used a variable resistance across a laser section with no externally applied bias. This resistance tuning method gave a tuning range of more than 7GHz while maintaining an intrinsically narrow linewidth. The optical frequency-locked loop was able to achieve DC frequency locking but unable to reduce laser linewidth. More work needs to be done to achieve enough phase noise reduction to see an appreciable reduction in linewidth.