We demonstrate the use of embedded CdS nanowires in improving spectral transmission loss and the low mechanical and electrical robustness of planar CdS window layer and thus enhancing the quantum efficiency and the reliability of the CdS-CdTe solar cells. CdS nanowire window layer enables light transmission gain at 300nm-550nm. A nearly ideal spectral response of quantum efficiency at a wide spectrum range provides an evidence for improving light transmission in the window layer and enhancing absorption and carrier generation in absorber. Nanowire CdS/CdTe solar cells with Cu/graphite/silver paste as back contacts, on SnO2/ITO-soda lime glass substrates, yield the highest efficiency of 12% in nanostructured CdS-CdTe solar cells. Reliability is improved by approximately 3 times over the cells with the traditional planar CdS counterpart. Junction transport mechanisms are delineated for advancing the basic understanding of device physics at the interface. Our results prove the efficacy of this nanowire approach for enhancing the quantum efficiency and the reliability in window-absorber type solar cells (CdS-CdTe, CdS-CIGS and CdS-CZTSSe etc) and other optoelectronic devices. We further introduce MoO3-x as a transparent, low barrier back contact. We design nanowire CdS-CdTe solar cells on flexible foils of metals in a superstrate device structure, which makes low-cost roll-to-roll manufacturing process feasible and greatly reduces the complexity of fabrication. The MoO3 layer reduces the valence band offset relative to the CdTe, and creates improved cell performance. Annealing as-deposited MoO3 in N2 reduces series resistance from 9.98 Ω/cm2 to 7.72 Ω/cm2, and hence efficiency of the nanowire solar cell is improved from 9.9% to 11%, which efficiency comparable to efficiency of planar counterparts. When the nanowire solar cell is illuminated from MoO3-x /Au side, it yields an efficiency of 8.7%. This reduction in efficiency is attributed to decrease in Jsc from 25.5mA/cm2 to 21mA/cm2 due to light transmission loss in the MoO3-x /Au electrode. Even though these nanowire solar cells, when illuminated from back side exhibit better performance than that of nanopillar CdS-CdTe solar cells, further development of transparent back contacts of CdTe could enable a low-cost roll-to-roll fabrication process for the superstrate structure-nanowire solar cells on Al foil substrate.

The progress of the silicon-based complementary-metal-oxide-semiconductor (CMOS) technology is mainly contributed to the scaling of the individual component. After decades of development, the scaling trend is approaching to its limitation, and there is urgent needs for the innovations of the materials and structures of the MOS devices, in order to postpone the end of the scaling. Atomic layer deposition (ALD) provides precise control of the deposited thin film at the atomic scale, and has wide application not only in the MOS technology, but also in other nanostructures. In this dissertation, I study rapid thermal processing (RTP) treatment of thermally grown SiO2, ALD growth of SiO2, and ALD growth of high-k HfO2 dielectric materials for gate oxides of MOS devices. Using a lateral heating treatment of SiO2, the gate leakage current of SiO2 based MOS capacitors was reduced by 4 order of magnitude, and the underlying mechanism was studied. Ultrathin SiO2 films were grown by ALD, and the electrical properties of the films and the SiO2/Si interface were extensively studied. High quality HfO2 films were grown using ALD on a chemical oxide. The dependence of interfacial quality on the thickness of the chemical oxide was studied. Finally I studied growth of HfO2 on two innovative interfacial layers, an interfacial layer grown by in-situ ALD ozone/water cycle exposure and an interfacial layer of etched thermal and RTP SiO2. The effectiveness of growth of high-quality HfO2 using the two interfacial layers are comparable to that of the chemical oxide. The interfacial properties are studied in details using XPS and ellipsometry.

Body mounted germanium substrate solar cell arrays form the faces of many small satellite designs to provide the primary power source on orbit. High efficiency solar cells are made affordable for university satellite programs as triangular devices trimmed from wafer scale solar cells. The smaller cells allow array designs to pack tightly around antenna mounts and payload instruments, giving the board design flexibility. One objective of this work is to investigate the reliability of solar cells attached to FR-4 printed circuit boards. FR-4 circuit boards have significantly higher thermal expansion coefficients and lower thermal conductivities than germanium. This thermal expansion coefficient mismatch between the FR-4 board and the components causes concern for the power system in terms of failures seen by the solar cells. These failures are most likely to occur with a longer orbital lifetime and an extended exposure to harsh environments. This work compares various methods of attaching solar cells to printed circuit boards, using solder paste alone and with a silicone adhesive, and considering the application of these adhesives by comparing the solder joints when printed by screen versus a stencil. An environmental test plan was used to compare the survivability and performance of the solar arrays.

The frequency demands of radiating systems are moving into the terahertz band with potential applications that include sensing, imaging, and extremely broadband communication. One commonly used method for generating and detecting terahertz waves is to excite a voltage-biased photoconductive antenna with an extremely short laser pulse. The pulsed laser generates charge carriers in a photoconductive substrate which are swept onto the metallic antenna traces to produce an electric current that radiates or detects a terahertz band signal. Therefore, analysis of a photoconductive antenna requires simultaneous solutions of both semiconductor physics equations (including drift-diffusion and continuity relations) and Maxwell’s equations. A multi-physics analysis scheme based on the Discontinuous-Galerkin Finite-Element Time-Domain (DGFETD) is presented that couples the semiconductor drift-diffusion equations with the electromagnetic Maxwell’s equations. A simple port model is discussed that efficiently couples the two equation sets. Various photoconductive antennas were fabricated using TiAu metallization on a GaAs substrate and the fabrication process is detailed. Computed emission intensities are compared with measured data. Optimized antenna designs based on the analysis are presented for a variety of antenna configurations.

Humidity measurement has been increasingly important in many industries and process control applications. This thesis research focus mainly on humidity sensor calibration and characterization. The humidity sensor instrumentation is briefly described. The testing infrastructure was designed for sensor data acquisition, in order to compensate the humidity sensor’s temperature coefficient, temperature chambers using Peltier elements are used to achieve easy-controllable stable temperatures. The sensor characterization falls into a multivariate interpolation problem. Neuron networks is tried for non-linear data fitting, but in the circumstance of limited training data, an innovative algorithm was developed to utilize shape preserving polynomials in multiple planes in this kind of multivariate interpolation problems.

Solar energy is an abundant renewable source, which is expected to play an increasing role in the grid's future infrastructure for distributed generation. The research described in the thesis focuses on the analysis of integrating multi-megawatt photovoltaics (PV) systems with battery energy storage into the existing grid and on the theory supporting the electrical operation of components and systems. The PV system is divided into several sections, each having its own DC-DC converter for maximum power point tracking and a two-level grid connected inverter with different control strategies. The functions of the battery are explored by connecting it to the system in order to prevent possible voltage fluctuations and as a buffer storage in order to eliminate the power mismatch between PV array generation and load demand. Computer models of the system are developed and implemented using the PSCADTM/EMTDCTM software.

An increasing need for effective thermal sensors, together with dwindling energy resources, have created renewed interests in thermoelectric (TE), or solid-state, energy conversion and refrigeration using semiconductor-based nanostructures. Effective control of electron and phonon transport due to confinement, interface, and quantum effects has made nanostructures a good way to achieve more efficient thermoelectric energy conversion. This thesis studies the two well-known approaches: confinement and energy filtering, and implements improvements to achieve higher thermoelectric performance. The effect of confinement is evaluated using a 2D material with a gate and utilizing the features in the density of states. In addition to that, a novel controlled scattering approach is taken to enhance the device thermoelectric properties. The shift in the onset of scattering due to controlled scattering with respect to sharp features in the density of states creates a window shape for transport integral. Along with the controlled scattering, an effective utilization of Fermi window can provide a considerable enhancement in thermoelectric performance. The conclusion from the results helps in selection of materials to achieve such enhanced thermoelectric performance. In addition to that, the electron filtering approach is studied using the Wigner approach for treating the carrier-potential interactions, coupled with Boltzmann transport equation which is solved using Rode's iterative method, especially in periodic potential structures. This study shows the effect of rapid potential variations in materials as seen in superlattices and the parameters that have significant contribution towards the thermoelectric performance. Parameters such as period length, height and smoothness of such periodic potentials are studied and their effect on thermoelectric performance is discussed. A combination of the above two methods can help in understanding the effect of confinement and key requirements in designing a nanostructured thermoelectric device that has a enhanced performance.

Gallium Nitride (GaN) high electron mobility transistors (HEMT) have superior performance characteristics compared to Silicon (Si) and Gallium Arsenide (GaAs) based transistors. GaN is a wide bandgap semiconductor which allows it to operate at higher breakdown voltages and power. Unlike traditional semiconductor devices, the GaN HEMT channel region is undoped and relies on the piezoelectric effect created at the GaN and Aluminum Gallium Nitride (AlGaN) heterojunction to create a conduction channel in the form of a quantum well known as the two dimensional electron gas (2DEG). Because the GaN HEMTs are undoped, these devices have higher electron mobility crucial for high frequency operation. However, over time and use these devices degrade in a manner that is not well understood. This research utilizes low frequency noise (LFN) as a method for analyzing changes and degradation mechanisms in GaN-on-Si devices due to gate stress. LFN is a useful tool for probing different regions of the device that cannot be measured through direct means. LFN generation in GaN HEMTs is based on the carrier fluctuation theory of 1/f noise generation which states fluctuations in the number of charge carriers results in conductance fluctuations that produce a Lorentzian noise spectrum. The summing Lorentzian noise spectra from multiple traps leads to 1/f and random telegraph signal (RTS) noise. The primary cause of carrier fluctuations are electron traps near the 2DEG and in the AlGaN bulk. These traps occur naturally due to dislocations and impurities in the manufacturing process, but new traps can be generated by the inverse-piezoelectric effect during gate stress. This thesis introduces noise and presents a circuit to bias the devices and measure gate and drain LFN simultaneously. Three measurements are performed before and after gate DC stress at three different temperatures: DC characterization, capacitance-voltage (C-V) measurements, and LFN measurements. The DC characteristics show an increase in gate leakage after stress caused by an increase in traps after degradation consistent with trap assisted tunneling. However, the leakage current on the drain and source side differ before and after stress leading to the conclusion that the source side of the gate is more sensitive to gate stress. Gate leakage current on the drain side is also sensitive to temperature due to thermionic trap assisted tunneling. Hooge parameter calculations agree with previous research. The LFN results show an increase in gate and drain noise power, SIg(f) and SId(f), in accordance with increased gate leakage current under cutoff bias. RTS noise is also observed to increase in frequency with increased temperature. Activation energies for RTS noise are extracted and qualitatively linked to trap depth based on the McWhorter trap model.

The mode-locked laser diode (MLLD) finds a lot of use in applications such as ultra high-speed data processing and sampling, large-capacity optical fiber communications based on optical time-division multiplexing (OTDM) systems. Integrating mode-locked lasers on silicon makes way for highly integrated silicon based photonic communication devices. The mode-locked laser being used in this thesis was built with Hybrid Silicon technology. This technology, developed by UC Santa Barbara in 2006, introduced the idea of wafer bonding a crystalline III- V layer to a Silicon-on-insulator (SOI) substrate, making integrated lasers in silicon chips possible. Furthermore, all mode-locked lasers produce phase noise, which can be a limiting factor in the performance of optical communication systems, specifically at higher bit rates. In this thesis, we design and discuss an impedance matching solution for a hybrid silicon mode-locked laser diode to lower phase noise and reduce the drive power requirements of the device. In order to develop an impedance matching solution, a thorough measurement and analysis of the impedance of the MLLD is necessary and was carried out. Then, a narrowband solution of two 0.1 pF chip capacitors in parallel is considered and examined as an impedance matching network for an operating frequency of 20 GHz. The hybrid silicon laser was packaged together in a module including the impedance- matching circuit for efficient RF injection. In conclusion, a 6 dB reduction of power required to drive the laser diode, as well as approximately a 10 dB phase noise improvement, was measured with the narrow-band solution. Also, looking ahead to possible future work, we discuss a step recovery diode (SRD) driven impulse generator, which wave-shapes the RF drive to achieve efficient injection. This novel technique takes into account the time varying impedance of the absorber as the optical pulse passes through it, to provide optimum pulse shaping.

It is well known that real op-amps do not share most of the desirable characteristics of an ideal one, particularly those of gain and output impedance. When presented with a capacitive load, such as a MOSFET or ADC, feedback in an op-amp circuit can quickly become unstable. This thesis studies and characterizes an op-amp’s output impedance and how its interaction with this type of load creates a parasitic pole which leads to instability. Applying ideas from feedback control theory, a model for studying the problem is developed from which a generalized method for compensating the undesirable circumstance is formulated. Even in a zero-input state, many real op-amps driving capacitive loads can experience unforced oscillations. A case study is performed with three commonly used devices. First, the output impedance is determined by its dependence on the unity-gain bandwidth, load capacitance, and oscillation frequency. It is fitted into a second-order feedback control model that allows for an analytical study of the problem. It is then shown that a carefully designed passive network can be introduced between the load and op-amp to obtain a properly damped system free of oscillation and well-behaved. Using a shunt resistor is a known and commonly used method for lowering an op-amp’s output impedance to gain stability. This work considers the converse addition of a series capacitor to instead lower the load capacitance seen by the op-amp, a seemingly complementary method that achieves the same goal. A generalized, composite compensation method is developed that uses both the shunt resistor and series capacitor– a strategy not yet found in literature. Relevant formulas for damping ratio and natural frequency are derived that allow the design of a passive compensation network. Furthermore, tradeoffs between compensation, voltage swing, current consumption, and power usage are considered. An emphasis is placed on comparing simulated versus real circuits to highlight the fact that any problem is much worse in real-life than in a simulation. SPICE models and programs aim to de-idealize certain device characteristics, but often cannot account for environmental conditions and manufacturing variance. Thus, an importance is placed on experimental verification guided by simulations.