Digital resampling is a process that converts a digital signal from one sampling rate to another. This process is performed by means of interpolating between the input samples to produce output samples at an output sampling rate. The digital interpolation process is accomplished with an interpolation filter.<p> The problem of resampling digital signals at an output sampling rate that is incommensurate with the input sampling rate is the first topic of this thesis. This problem is often encountered in practice, for example in multiplexing video signals from different sources for the purpose of distribution. There are basically two approaches to resample the signals. Both approaches are thoroughly described and practical circuits for hardware implementation are provided. A comparison of the two circuits shows that one circuit requires a division to compute the new sampling times. This time scaling operation adds complexity to the implementation with no performance advantage over the other circuit, and makes the 'division free' circuit the preferred one for resampling.<p> The second topic of this thesis is performance analysis of interpolation filters for Quadrature Amplitude Modulation (QAM) signals in the context of timing recovery. The performance criterion of interest is Modulation Error Ratio (MER), which is considered to be a very useful indicator of the quality of modulated signals in QAM systems. The methodology of digital resampling in hardware is employed to describe timing recovery circuits and propose an approach to evaluate the performance of interpolation filters. A MER performance analysis circuit is then devised. The circuit is simulated with MATLAB/Simulink as well as implemented in Field Programmable Gate Array (FPGA). Excellent agreement between results obtained from simulation and hardware implementation proves the validity of the methodology and practical application of the research works.

Digital resampling is a process that converts a digital signal from one sampling rate to another. This process is performed by means of interpolating between the input samples to produce output samples at an output sampling rate. The digital interpolation process is accomplished with an interpolation filter.<p> The problem of resampling digital signals at an output sampling rate that is incommensurate with the input sampling rate is the first topic of this thesis. This problem is often encountered in practice, for example in multiplexing video signals from different sources for the purpose of distribution. There are basically two approaches to resample the signals. Both approaches are thoroughly described and practical circuits for hardware implementation are provided. A comparison of the two circuits shows that one circuit requires a division to compute the new sampling times. This time scaling operation adds complexity to the implementation with no performance advantage over the other circuit, and makes the 'division free' circuit the preferred one for resampling.<p> The second topic of this thesis is performance analysis of interpolation filters for Quadrature Amplitude Modulation (QAM) signals in the context of timing recovery. The performance criterion of interest is Modulation Error Ratio (MER), which is considered to be a very useful indicator of the quality of modulated signals in QAM systems. The methodology of digital resampling in hardware is employed to describe timing recovery circuits and propose an approach to evaluate the performance of interpolation filters. A MER performance analysis circuit is then devised. The circuit is simulated with MATLAB/Simulink as well as implemented in Field Programmable Gate Array (FPGA). Excellent agreement between results obtained from simulation and hardware implementation proves the validity of the methodology and practical application of the research works.

Timing recovery is the processing of synchronizing the sampler with the received analog signal. Sampling at the wrong times can have a devastating impact on performance. Conventional timing recovery techniques are based on a decision-directed phase-locked loop (PLL). They are adequate only when the operating signal-to-noise ratio (SNR) is sufficiently high, but recent advances in error-control coding have made it possible to communicate reliably at very low SNR, where conventional techniques fail. This thesis develops new techniques for timing recovery that are capable of working at low SNR. We propose a new timing recovery scheme based on per-survivor processing (PSP), which jointly performs timing recovery and equalization, by embedding a separate PLL into each survivor of a Viterbi algorithm. The proposed scheme is shown to perform better than conventional scheme, especially when the SNR is low and the timing error is large. An important advantage of this technique is its amenability to real-time implementation. We also propose a new iterative timing recovery scheme that exploits the presence of the error-control code; in doing so, it can perform even better than the PSP scheme described above, but at the expense of increased complexity and the requirement of batch processing. This scheme is realized by embedding the timing recovery process into a trellis-based soft-output equalizer using PSP. Then, this module iteratively exchanges soft information with the error-control decoder, as in conventional turbo equalization. The resulting system jointly performs the functions of timing recovery, equalization, and decoding. The proposed iterative timing recovery scheme is shown to perform better than previously reported iterative timing recovery schemes, especially when the timing error is severe. Finally, performance analysis of iterative timing recovery schemes is difficult because of their high complexity. We propose to use the extrinsic information transfer (EXIT) chart as a tool to predict and compare their performances, considering that the bit-error rate computation takes a significant amount of simulation time. Experimental results indicate that the system performance predicted by the EXIT chart coincides with that obtained by simulating data transmission over a complete iterative receiver, especially when the coded block length is large.

We propose to develop new non-data aided (NDA) digital feedforward symbol timing estimators for linear and nonlinear modulations, with a view to reducing the sampling rate of the estimators. The proposed estimators rely on the fact that sufficient statistics exist for a signal sampled at the Nyquist rate. We propose an ad hoc extension to the timing estimator based on the log nonlinearity which performs better than existing estimators at this rate when the operating signal-to-noise ratio (SNR) and the excess bandwidth are low. We propose another alternative estimator for operating at the Nyquist rate that has reduced self-noise at high SNR for large rolloff factors. This can be viewed as an extension of the timing estimator based on the square law nonlinearity. For continuous phase modulations (CPM), we propose two novel estimators that can operate at the symbol rate for MSK type signals. Among the class of NDA feedforward timing estimators we are not aware of any other estimator that can function at symbol rate for this type of signals. We also propose several new estimators for the MSK modulation scheme which operate with reduced sampling rate and are robust to carrier frequency offset and phase offset.

Symbol timing recovery is an important function of any digital receiver. In the wireless mobile data field the task of establishing accurate symbol timing at the receiver is complicated by the time varying channel. This time varying channel also makes the use of coherent modulation schemes significantly more difficult. This is one of the major reasons that almost all existing mobile wireless digital standards utilise some form of differential modulation and detection. This thesis takes a primarily practical approach to the investigation of timing and phase estimation problems. The main focus of the work is on the comparison of three existing all digital timing synchronisation algorithms, two of which were originally designed for the AWGN channel, and the third was designed from ML principles for the Rayleigh fading channel. In order to test these sub-systems in the wider context of receiver performance, a pilot symbol assisted (PSAM) receiver was simulated to compare the effects of the different synchronisers on receiver steady state performance. Finally, because the real time implementation aspects of software radio are of considerable interest to the author, some attempt has been made to migrate the MATLAB synchronisation simulations to a real time DSP platform, specifically the TMS320C6701 Texas Instruments floating point device.

This thesis presents a timing error detector (TED) used in the symbol timing synchronization subsystem for digital communications. The new timing error detector is designed to minimize the probability of symbol decision error, and it is called minimum symbol error rate TED (MSERTED). The new TED resembles the TED derived using the maximum likelihood (ML) criterion but gives rise to faster convergence relative to MLTED. The new TED requires shorter training sequences for symbol timing recovery. The TED operates on the outputs of the matched filter and estimates the timing offset. The S-curve is used as a tool for analyzing the behavior of the TEDs. The faster convergence of the new TED is shown in simulation results as compared to MLTED. The new TED works well for any two-dimensional constellation with arbitrarily shaped decision regions.

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The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field.<p> A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market.<p> Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. <p> The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. <p> A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation.<p> Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. <p> A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection.

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field.<p> A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market.<p> Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. <p> The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. <p> A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation.<p> Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. <p> A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection.

Ultra-wideband (UWB) is a wireless system which transmits signals across a much wider frequency spectrum than traditional wireless systems. The impulse radio (IR) UWB technique uses ultra-short duration pulses of nanoseconds or less. The objective of this thesis is to provide the design, implementation and testing of the timing recovery between the transmitter and receiver of the recently emerging differential code-shifted reference (DCSR) Impulse radio (IR) ultra-wideband (UWB) system. A new non-coherent energy detection based technique and its algorithm are proposed for timing recovery by means of a phase-locked loop (PLL) circuit. Simulations are presented first to verify the proposed algorithm. Then, it is implemented and tested in the Lattice ECP2 field-programmable gate array (FPGA) evaluation board with VHDL codes (a VHSIC hardware description language). The simulation and implementation results show that the proposed timing recovery scheme can be effectively achieved without much error.