This thesis presents a low power consumption and low phase noise CMOS integer-N frequency synthesizer, and it bases on a charge-pump PLL topology. The frequency synthesizer can be used for IEEE 802.16b unlicensed band of WiMAX(World Interoperability for Microwave Access) from 5.725GHz to 5.825GHz. It provides the one ration frequency ranged from 5.13GHz to 5.22GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage-controlled oscillator, and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator to achieve low power consumption and low phase noise. Moreover divider is implemented by an optimal extended true single-phase clock-base prescaler. It can achieve high-resolution frequency operation and reduction of power consumption. This chip is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The whole chip area is 1.1 mm2.

This dissertation presents a novel [delta sigma] analog-to-digital converter architecture which replaces the operational amplifier-based integrator with a pair of tunable oscillators. A switched-capacitor V-I converter is used to combine the input voltage with a feedback DAC output and convert it into a current for two pseudo-differential current-controlled oscillators. The oscillator outputs are counted with a digital counter, and a digital back-end [delta sigma] modulator is used to truncate the high-resolution counter outputs for the feedback DAC path. This architecture has compelling advantages in deep sub-micron and emerging technologies where supply voltages are decreasing to a point that traditional analog architectures are no longer feasible. Additionally, this architecture takes advantage of the increased speed in these short-channel technologies. Measured results on a 6.08mW prototype in TSMC 0.18um achieving 63.5dB in a 2MHz bandwidth are presented. / text

abstract: An investigation of phase noise in amplifier and voltage-controller oscillator (VCO) circuits was conducted to show that active direct-current (DC) bias techniques exhibit lower phase noise performance than traditional resistive DC bias techniques. Low-frequency high-gain amplifiers like those found in audio applications exhibit much better 1/f phase noise performance and can be used to bias amplifier or VCO circuits that work at much higher frequencies to reduce the phase modulation caused by higher frequency devices. An improvement in single-side-band (SSB) phase noise of 15 dB at offset frequencies less than 50 KHz was simulated and measured. Residual phase noise of an actively biased amplifier also exhibited significant noise improvements when compared to an equivalent resistive biased amplifier. / Dissertation/Thesis / M.S. Electrical Engineering 2010

Ce travail concerne l'étude et la réalisation de stratégies d'auto-test intégrées pour VCO radiofréquence (RF). La complexité des circuits intégrés RF devient un obstacle pour la mesure des principaux blocs RF des chaines de transmission/réception. Certains nœuds ne sont pas accessibles, l'excursion en tension des signaux baisse et les signaux haute fréquence ne peuvent pas être amenés à l'extérieur de la puce sans une forte dégradation. Le s techniques habituelles de test deviennent très couteuses et lentes. Le test pour le wafer-sort est étudié en premier. La solution proposée est la mise en œuvre d'une stratégie d'auto-test intégrée (BIST) qui puisse discriminer entre circuits sans fautes et circuits avec fautes pendant le wafer-test. La méthodologie utilisée est le test structurel. La couverture des fautes est étudiée pour connaitre la quantité à capter au niveau intégré afin de maximiser la probabilité de trouver tous les défauts physiques dans le VCO. Le résultat de cette analyse montre que la couverture des fautes est maximisée quand la tension crête-crête en sortie du VCO est captée. La caractérisation complète (validation de la puce et process-monitoring) du VCO est étudiée dans la deuxième étape. Les informations à extraire de la puce sont: amplitude des signaux, consommation du VCO, fréquence d'oscillation, gain de conversion (Kvco) et une information à propos du bruit de phase. Un démonstrateur pour le test au niveau wafer est réalisé en technologie ST CMOS 65nm. Le démonstrateur est composé d'un VCO 3.5GHz (le circuit sous test), un LDO, une référence de tension indépendante de température et variations d'alimentation, un capteur de tension crête-crête et un comparateur. Le capteur Vpp donne en sortie une information DC qui est comparée avec une plage de valeurs acceptables. Le BIST donne en sortie une information numérique pass/fail. / This work deals with the study and the realization of Built-In Self-Tests (BIST) for RF VCOs (Voltage Controlled Oscillators) The increasing complexity of RF integrated circuits is creating an obstacle for the correct measurement of the main RF blocks of any transceiver. Some nodes are not accessible, the voltage excursion of the signals is getting lower and lower and high frequency signals cannot be driven off the die without a main degradation. The common test techniques become then very expensive and time consuming. The wafer sort is firstly approached. The proposed solution is the implementation of a BIST strategy able to discriminate between faulty and good circuits during the wafer test. The chosen methodology is the structural test (fault-oriented). A fault coverage campaign is carried out in order to find the quantity to monitor on-chip that maximizes the probability to find all possible physical defects in the VCO. The result of the analysis reveals that the fault coverage is maximized if the peak-to-peak output voltage is monitored. The complete on-chip characterization of the VCO is then addressed, for chip validation and process monitoring. The information that need to be extracted on-chip concern: amplitude of the signal, consumption of the VCO, frequency of oscillation, its conversion gain (voltage-to-frequency) and eventually some information on the phase noise. A silicon demonstrator for wafer sort purposes is implemented using the ST CMOS 65nm process. It includes a 3.5GHz VCO, an LDO, a temperature and supply-voltage independent voltage reference, a peak-to-peak voltage detector and a comparator. The Vpp detector outputs a DC-voltage that is compared to a predefined acceptance boundary. A logic pass/fail signal is output by the BIST. The attention is then turned to the study of the proposed architecture for an on-chip frequency-meter able to measure the RF frequency with high accuracy. Behavioral simulations using VHDL-AMS lead to the conclusion that a TDC (Time-to-Digital Converter) is the best solution for our goal. The road is then opened to the measure of long-time jitter making use of the same TDC.

CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on "split ADC" architecture. Each of the two split channels, ADC "A" and "B", contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs' sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADC’s LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate).

No description available.

To support the large growth in wireless devices, such as personal data assistants (PDAs), wireless local area network (WLAN) enabled laptop computers, and intelligent transportation systems (ITS), the FCC allocated three high-frequency bands for unlicensed operation. Of particular interest is the 5-6 GHz Unlicensed National Information Infrastructure (UNII) band intended to support high-speed WLAN applications. The UNII band is further split into three smaller 100 MHz sub-bands: 5.15 - 5.25 GHz; 5.25-5.35 GHz; and 5.725-5.825 GHz. VCOs that can be switched between each of the three UNII sub-bands offer flexibility and optimum phase-locked loop (PLL) design versus non-switchable VCOs. This work presents switched-tank voltage controlled oscillators (VCOs) designed in Motorolaà ­s 0.18 à µm HIP6WRF BiCMOS process that could be used in multiband receivers covering the three UNII sub-bands. The first VCO was optimized for low power consumption. The VCO draws a total of 6.75 mA from a 1.8 V supply including buffer amplifiers. The VCO is designed with a switched-capacitor LC tank circuit that can switch to two center frequencies, 5.25 GHz and 5.775 GHz, with 200 MHz of varactor-supplied tuning range. The simulated output voltage swing is 2.0 V peak-to-peak and is kept constant between sub-bands by an active PMOS load integrated into the biasing circuitry. The second VCO was optimized for a high output voltage swing by replacing the current biasing circuit with a degenerating inductor. This design targeted three center frequencies, 5.2 GHz, 5.3 GHz, and 5.775 GHz, with 100 MHz of tuning range. This design has an output peak-to-peak voltage swing of 5.2 V but consumes an average of 16.5 mA from a 1.8 V supply. The two fabricated circuits exhibit tuning ranges similar to the simulated results; however, the center frequencies of each decrease due to interconnect parasitics there were unaccounted for in the designs. The measured center frequencies are 4.4 GHz and 5.37 GHz for the first design, and 4.4 GHz and 4.7 GHz for the second design (with one state inoperative due to a faulty switch). The phase noise of the fabricated VCO designs was limited primarily by the low quality factor (Q-factor) of the on-chip LC tank circuits. Oscillators referenced with high-Q off-chip components such as quartz crystal references and surface acoustic wave (SAW) resonators in a PLL can exhibit much improved performance; however, these off-chip components add packaging/assembly cost and higher bill of materials, impedance matching issues, and parasitics that can significantly affect performance for RF applications. Thus, there is tremendous incentive for integrating high-Q components on-chip with the eventual goal of consolidating all of the RF/analog/digital components onto a single wireless-enabled chip, commonly called RF system-on-a-chip (SoC). Microelectromechanical (MEM) resonators have received significant attention based on their ability to provide high on-chip Q-factors at RF frequencies using fabrication techniques that are compatible with modern IC processes. MEM resonators transduce electrical signals into extremely low-loss mechanical vibration and vice versa. Consequently, this thesis also describes the modeling, simulation, and fabrication of contour-mode disk-shaped MEM resonators. This resonator geometry is capable of providing high-Q oscillation at frequencies exceeding 1 GHz at sizes easily within the limits of modern photolithography techniques. Finite element analysis is used to predict the frequency response of disk resonators under various operating conditions and to determine variables that are most critical to the resonator design. A silicon-on-insulator (SOI) fabrication process for constructing the disk is also discussed. Finally, the possible future integration of MEM resonators with multiband VCOs in a common IC process is proposed. / Master of Science

Decreasing reserves of natural resources drives the oil and gas industry to drill deeper and deeper to reach unexploited wells. Coupled with the demand for substantial real-time data transmission, the need for high speed electronics able to operating in harsher ambient environment is quickly on the rise. This paper presents a high temperature VCO for downhole communication system. The proposed VCO is designed and prototyped using 0.25 μm GaN on SiC RF transistor which has extremely high junction temperature capability. Measurements show that the proposed VCO can operate reliably under ambient temperature from 25 °C up to 230 °C and is tunable from 328 MHz to 353 Mhz. The measured output power is 18 dBm with ±1 dB variations over entire covered temperature and frequency range. Measured phase noise at 230 °C is from -121 dBc/Hz to -109 dBc/Hz at 100 KHz offset. / Master of Science

The explosive growth in wireless communications has led to an increased demand for wireless products that are cheaper, smaller, and lower power. Recently there has been an increased interest in using CMOS, a traditional digital and low frequency analog IC technology, to implement RF components such as mixers, voltage controlled oscillators (VCOs), and low noise amplifiers (LNAs). Future mass-market RF links, such as BlueTooth, will require the potentially low-cost single-chip solutions that CMOS can provide. In order for such single-chip solutions to be realized, RF circuits must be designed that can operate in the presence of noisy digital circuitry. The voltage controlled oscillator (VCO), an important building block for RF systems, is particularly sensitive when exposed to an electrically noisy environment. In addition, CMOS implementations of VCOs have been hampered by the lack of high-quality integrated inductors. This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS VCO. The circuit is intended as a vehicle for future mixed RF/digital noise characterization. The circuit was implemented in a 0.35 μm single poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The oscillator uses a complementary negative transconductance topology. This oscillator circuit is analyzed as a negative-resistance oscillator. Monolithic inductors are designed using full-wave electromagnetic field solver software. The design of an "inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a discussion of the effects of varactor nonlinearity on VCO performance. I-MOS varactors are shown to have substantially improved tuning range (and tuning curve linearity) over conventional MOS varactors. Practical issues pertaining to CMOS VCO circuit design, layout, and testing are also discussed. The characterization of the VCO and the integrated passives is presented. The VCO achieves a best-case phase noise of -106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V supply. This represents excellent performance for CMOS oscillator designs reported at this frequency. Finally, several recommendations for improvements in oscillator performance and characterization are discussed. / Master of Science

As the oil and gas industry continues to explore higher temperature environments, electronics that operate at those temperatures without additional cooling become critical. Additionally, current communications systems cannot support the higher data-rates being offered by advancements in sensor technology. An RF modem would be capable of supplying the necessary bandwidth to support the higher data-rate. A voltage-controlled oscillator is an essential part of an RF modem. This thesis presents a 2.336-2.402 GHz voltage-controlled oscillator constructed with 0.25 μm GaN-on-SiC technology high electron mobility transistor (HEMTs). The measured operating temperature range was from 25°C to 225°C. A minimum tuning range of 66 MHz, less than 20% variation in output power, and harmonics more than 20 dB down from the fundamental is observed. The phase noise is between -88 and -101 dBc/Hz at 100 kHz offset at 225°C. This is the highest frequency oscillator that operates simultaneously at high temperatures reported in literature. / Master of Science / The oil and gas industry require communications systems to transmit data collected from sensors in deep wells to the surface. However, the temperatures of these wells can be more than 210 °C. Traditional Silicon based circuits are unable to operate at these temperatures for a prolonged period. Advancements in wide bandgap (WBG) semiconductor devices enable entrance into this realm of high temperature electronics. One such WBG technology is Gallium Nitride (GaN) which offers simultaneous high temperature and high frequency performance. These properties make GaN an ideal technology for a high temperature RF modem. A voltage-controlled oscillator is an essential part of a RF modem. This thesis demonstrates a GaN-based 2.36 GHz voltage-controlled oscillator (VCO) whose performance has been measured over a temperature range of 25°C-225°C. This is the highest frequency oscillator that operates simultaneously at high temperatures reported in literature.