Orientadores: Mario Lucio Cortes, Guido Costa Souza de Araujo / Tese (doutorado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-07-25T20:10:08Z (GMT). No. of bitstreams: 1 Centoducatte_PauloCesar_D.pdf: 4355803 bytes, checksum: 020add3207bd3cd0ecf23cfa65c2abea (MD5) Previous issue date: 2000 / Resumo: A redução no tamanho dos programas tem sido um fator importante no projeto de sistemas embarcados modernos voltados à produção em larga escala. Este problema tem direcionado grandes esforços em projetos de processadores que se utilizam de um conjunto de instruções com formato de tamanho reduzido (ex. ARM Thumb e MIPS16) ou que sejam capazes de executarem códigos comprimidos (ex. CCRP, CodePack, etc). Muitos dos trabalhos publicados na literatura têm sido realizados para arquiteturas RISC. Este trabalho propôe um algoritmo de compressão de programas e uma máquina de descompressão para arquiteturas RISC e DSP. O algoritmo utiliza como símbolos para a compressão as árvores de expressão do programa. Resultados experimentais, baseados em programas do SPECInt95 executando em processador MIPS R4000, mostraram uma razão de compressão média, para os programas, de 27,2% e uma razão de compressão de 60,7% quando a área ocupada pela máquina de descompressão é considerada. Resultados experimentais para programas típicos de aplicações para DSPs, executando em um processador TMS320C25, mostraram uma razão de compressão média, para os programas, de 28% e de 75% quando a área da máquina de descompressão é considerada. As máquinas de descompressão foram sintetizadas usando-se bibliotecas standard cell da AMS, para a tecnologia CMOS de 0,6 11m e 5 volts. Simulações da máquina de descompressão mostraram uma freqüência mínima de operação de 90MHz (R4000) e de 130MHz (TMS320C25) / Abstract: Reducing program size has become an important goal in the design of modern embedded systems targeted to mass production. This problem has driven a number of efforts aimed at designing processors with shorter instruction formats (e.g. ARM Thumb and MIPS16), or that are able to execute compressed code (e.g. CCRP, CodePack, etc). Much of the published work has been directed towards RISC architectures. This work proposes acode compression algorithm and a decompression engine for embedded RISC and DSP architectures. In the algorithm, the encoded symbols are the program expression trees. Experimental results, based on SPEClnt95 programs running on the MIPS R4000, reveal an average compression ratio of 27.2% to the programs and 60.7% if the area of the decompression engine is considered. Experimental results for typical DSP programs running on the TMS320C25 processor reveal an average compression ratio of 28% to the programs and 75% if the area of the decompression engine is considered. The decompression engines are synthesized using the AMS CMOS standard cell library and a 0.6 p,m 5 volts technology. Gate leveI simulation of the decompression engines reveals minimum operation frequencies of 90MHz (R4000) and 130MHz (TMS320C25) / Doutorado / Doutor em Ciência da Computação

Image convolution is a common algorithm that can be found in most graphics editors. It is used to filter images by multiplying and adding pixel values with coefficients in a filter kernel. Previous research work have implemented this algorithm on different platforms, such as FPGAs, CUDA, C etc. The performance of these implementations have then been compared against each other. When the algorithm has been implemented on an FPGA it has almost always been with a single convolution. The goal of this thesis was to investigate and in the end present one possible way to implement the algorithm with 16 parallel convolutions on a Xilinx Spartan 6 LX9 FPGA and then compare the performance with results from previous work. The final system performs better than multi-threaded implementations on both a GPU and CPU.

This design accomplished Tic-Tac-Toe game on Xilinx Spartan-IIE FPGA platformin VHDL. Firstly, designing the circuits and wiring on experiment board. Secondly,designing the algorithm and programming it in Active-HDL. Thirdly, synthesizingit in Synplicity Synplify Pro and then implementing it in Xilinx ISE developingsuite. Finally download it onto FPGA to run it. This design allows two players to play Tic-Tac-Toe game on the experiment board.Pressing the key, the corresponding LED will be light up to represent thechessman. There are two LEDs indicate whose turn next is. If the grid one wantsto place chessman has been taken up, then LCD will alarm it and ask the playerto replace it. The first player who forms 3 chessmen in a row, column or diagonalwins, LCD will display it and the three LEDs in the winning line will blink. If nobody wins after filling the whole chessboard, then LCD displays draw.

This is a master thesis in the field of information security. The problem area addressed is how to efficiency implement encryption and decryption of biometric image data in a FPGA. The objective for the project was to implement AES (Advanced Encryption Standard ) encryption in a Xilinx Kintex-7 FPGA with biometric image data as the application. The method used in this project is Design Science Research Methodology, in total three design and development iterations were performed to achieve the project objectives. The end result is a FPGA platform designed for information security research with biometric image as application. The FPGA developed in this project, is the first fully pipelined AES encryption/decryption system to run physically in a Kintex-7 device. The encryption core was made by Dr. Qiang Liu and his team while the fully pipelined decryption core was designed in this project. The AES encryption/ decryptions was further optimized to support image application by adding Cipher-block chaining to both the encryption and decryption. The performance achieved for the system was 40 GB/s throughput, 5.27 Mb/slice efficiency with a power performance of 286 GB/W. The FPGA platform developed in this project is not only limited to AES, other cryptography standards can be implemented on the platform as well. / <p>Validerat; 20140619 (global_studentproject_submitter)</p>

This diploma thesis deals with the problem of high-speed communication security which leads to the usage of hardware accelerators, in this case high-speed FPGA NICs. Work with simplification of development of FPGA hardware accelerator applications using the P4 to VHDL compiler. Describes extension of compiler of cryptographic external objects support. Teoretical introduction of the thesis explains basics of P4 language and used technologies. Describes mapping of external objects to P4 pipeline and therefore to FPGA chip. Subsequently deals with cryptographic external object, compatible wrapper implementation and verification of design. Last part describes implementation and compiler extension, cryptographic external object support and summarizes reached goals.

This study describes the platform Atmel FPSLIC, which is created by means of the logic arrays FPGA and the micro-sequencer controller AVR. The developmental kit STK594 is described here as well, with its programming possibilities, as for the logic arrays FPGA, as for the micro-sequencers AVR. Also the separate circuit AT94K is described there. This circuit can be programmed by the language VHDL (the field FPGA), or by means of the assembler and language C for the micro-sequencer. All this can be integrated into the one output file by means of program System Designer, comprising a set of software tools for given programming languages and for generation of the whole circuit. Furthermore, the study describes a simple application for the both platform parts. Also the description of the dynamic reconfiguration of the circuit gate part is included.

This master’s thesis deal’s with VHDL programming language, ISE Webpack design system and PicoBlaze microprocessor. The thesis describes essentials of VHDL programming language and its application. A simple introduction to ISE Webpack design environment is given. The thesis describes common peripherals and the PicoBlaze processor is described too, including its parameters and implementation aspects. Finally the thesis describes IP generator for generating complex FPGA design including Picoblaze processor.

In this thesis I aim at a design of the laboratory kit and study ways how to programme CPLD devices made by Altera company. The product is used for development and demonstration of applications in CPLD devices made by Altera company. The kit is designed for Altera programming cables and Presto (made by ASIX). Input signals are implemented by a set of switches and buttons on the board. Output states are displayed by LED diods, possibly connected to multiplex the display. The user can connect to external devices via external inputs. Thesis is also aimed at the design PCB of the laboratory kit, subsequent production, recovery and verification of compatibility ALTERA and PRESTO programmers. End of the thesis aims on working with the Quartus II design environment. In particular, it is a guide to working with templates and simulation of VHDL designs.

Goal of this master thesis is to introduce and bring up basics and principles of NetCOPE framework in many details using "first approach" method for exploration of its internal structures - mainly focusing on application core using VHDL for focus itself. Furthermore, this knowledge is used for design and implementation of filtration system for network traffic with more details within phase of design in VHDL language.

The goal of this project is to design a signal and data logger, which captures analog and digital signals with very long record time. The device supports multichannel complex triggering, a real-time oscilloscope-like mode and an offline mode for analyzing of previously sampled data. This project contains detailed analysis of the topic, description of hardware and software solutions and used methods. The thesis also contains verification tests and measurements. This device will be mainly used for hardware debugging of microprocessor based applications.