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yes / Engineering undergraduates not only need to learn facts, but also how to be creative in the open-ended situations they will encounter in their professional careers. Our final year Honours module gives students a grounding in digital systems design, mainly using VLSI for design entry and simulation. The second half of our module is a design exercise, which has straightforward aspects, but which allows motivated students to undertake progressively open-ended investigations. Our educational framework is guided by recommendations of professional bodies promoting excellence and encouragement of creativity in engineering development. (C) 2013 The Authors. Published by Elsevier Ltd.

Validating DSP circuits modeled in VHDL involves generating test data, creating VHDL test benches, and simulating the test benches including models under test (MUTs). This is a laborious and time-consuming process. Therefore, it is desirable to develop a high level approach to automating and planning these tasks. This dissertation presents a high level test planning system for functional validation of VHDL DSP models. The system requirements parameterized from the specifications constitute the input space and serve as generics of test benches. Library-based test benches are developed using high level design tools. A test planning framework uses a goal tree structure as a vehicle of planning and documenting the testing activities. In a goal tree, test goals are given based on the specifications and test groups are defined to satisfy the test goals. Test groups partially constrain the system requirements and thus partition the input space into smaller and more manageable subspaces. A set of test strategies are then applied to the test groups for efficient test case design. Each test case is mapped to a configuration declaration of the test bench. The test bench is then simulated to generate test vectors against which the MUT is tested. The MUT response is compared with the gold response by a comparator and verdicts are reached by test oracles. An integrated test planning software system has been developed for test planning and test automation based on this approach. As an illustration of this approach, this dissertation uses the Synthetic Aperture Radar system as a case study. Completeness and effectiveness of the generated test set are evaluated. This dissertation also discusses approaches to hierarchical faulty module isolation for hierarchical circuits. Exposability is proposed to measure the extent that signal values are revealed to the tester and is used as the cost function for the faulty module search problem. An expanded goal tree which explores the functional and structural aspects of a hierarchical circuit is also presented. / Ph. D.

This thesis describes the design and implementation of a hardware synthesis system based on design descriptions provided in VHDL. Several aspects of the synthesis problem are examined. These include the design of an internal format to represent multiple levels of design information, algorithms for synthesis, optimizations, and verification of the synthesis process. Key features of this system include the ability to synthesize models that span a wide range of design description abstraction levels. The synthesis system internal format contains data structures for algorithmic, dataflow, as well as structural VHDL constructs. This framework for performing synthesis over a wide range of abstraction levels is the novel feature of this system. Optimizations for register-transfer level (dataflow) models are discussed along with their implementation. The design and implementation of the synthesis library, which contains information about the hardware components available to perform the synthesis, is also discussed. The output of the synthesis system is in the form of two files, an RNL format netlist and a purely structural VHDL netlist. In order to produce the actual hardware layout, the RNL netlist must be input to VPNR, a standard cell place and route system. The structural VHDL may be simulated to verify the synthesis process. Results of mixed level synthesis are provided. / Master of Science

This thesis describes the development of the Hierarchical Behavioral Test Generator (HBTG) for the testing of VHDL behavioral models. HBTG uses the Process Model Graph of the VHDL behavioral model as the base for test generation. Test sets for individual processes of the model are precomputed and stored in the design library. Using this information, HBTG hierarchically constructs a test sequence that tests the functionality of the model. The test sequence generated by HBTG is used for the simulation of the model. Various features present in HBTG and the implementation of the algorithm are discussed. The idea of an effective test sequence for a VHDL behavioral model is proposed. A system is presented to evaluate the quality of the test sequence generated by the algorithm. Test sequences and coverage results are given for several models. Some suggestions for future improvements to the tools are made. The HBTG forms part of a complete CAD system for rapid development and testing of VHDL behavioral models. / Master of Science

The enhancement of a CAD tool called Modeler's Assistant is discussed. This tool allows VHDL behavioral models to be developed more rapidly than with traditional techniques. The limitations present in the previous version of the tool (Version 2) are discussed. The correction of these limitations and the enhancement of Modeler's Assistant are the focus of the work described in this thesis. New features present in the enhanced version of Modeler's Assistant (Version 3) include the ability to create and maintain a library of parameterized process primitives and the ability to graphically represent hierarchy in VHDL behavioral models through the use of supernodes. Other enhancements that allow more features of the VHDL language to be used in Modeler's Assistant are described. Several examples that illustrate the use of these enhanced features are presented. / Master of Science

Behavioral modeling of RF systems with VHDL is considered and a modeling methodology is developed for modeling the I/O response of these systems. A Pulsed Doppler radar system is chosen as a representative system, and a VHDL model for this system is presented. The modeling approach and the working of the model are explained, and some example runs are provided. Some problems that are posed by VHDL in attempting to model the behavior of RF systems are discussed, along with the solutions that we adopted. A fault diagnosis methodology for systems of this type that uses information about the behavior of the system (extracted from a VHDL model of the system) is discussed, and an example is presented. / Master of Science