This thesis contains information about fast measuring card design for data processing from NQR measuring probe. The overall purpose is to create functional prototype of measuring card. Thesis describes suitable design of PCB having regard to EMC. There are information abou digital signal processing, using algorithms DFT and FFT. The thesis contains information about FPGA and there are rules, how to program FPGA correctly. In the practical part of the thesis, there are information about PCB design of ADC and DAC. There are also information about design of program for FPGA and control application for PC.

This diploma thesis is a part of a project of two students. The aim of the project is to design safer electronics for the unstable balancing vehicle HUMMER and implementation of advanced diagnostics and fault detection. In the first part of the project we analysed the original vehicle using the FMEA analyse and created a new concept of the vehicle. The second part of the project describes a new hardware. I designed and tested the power electronics, control unit and supplies. The outputs of the work are prototypes which allow testing a new concept.

The thesis describes the process of transformation of the behavior of processor described in C language into VHDL language. Individual steps of automatized transformation are compared to manual design of processor. The thesis highlights advantages of the internal representation of program in the form of graph. Optimizations based on various factors are introduced in this thesis. One of them are algebraic modifications of expressions. The time of computation or space requirements of the circuit can be lowered by proper aplication of properties of math operators - associativity, comutativity and distributivity. Special attention is payed to optimizations, that make use of parallelism of operations for the process of planning. Algorithms of time-constrained scheduling and resource-constrained scheduling are discussed. The end of this thesis is devoted to resource allocation.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes an approach to the implementation of an IF sampling digital receiver for low data rate command and telemetry applications in the NASA Goddard Spaceflight Tracking and Data Network (STDN) and Air Force Space-Ground Link System (SGLS). The digital design is targeted for an FPGA-based implementation and was written entirely in VHDL. Several size and clock reduction techniques are described which were utilized due to limited gate-array resources and power. The system-level design architecture is described followed by a discussion of algorithms and performance of critical stages in the receiver chain. Bit error performance of the prototype receiver is also presented. Finally, although this design is specifically targeted for a narrowband command and telemetry application, the methodology forms the basis of a configurable receiver for higher data rate applications.

FPGA stands for Field Programmable Gate Array and it is a technology that has been on the rise the last decades. With a decrease in size of the logic elements commercially available products have started to have more built-in functionality in one package and by being reprogrammable makes the system a powerful competitor among its neighbors. FPGA technology in comparison with Digital Signal Processing technology is generally interesting because of the parallelism of the programming that can be made. This allows for more operations in less time. In this thesis a system is developed to control power converters with control signals in high frequency. A previous project is used as a base and a toolchain of new components are implemented to create a new, more generic system. The previous system is evaluated and a new protocol for communication is developed. The toolchain with the necessary control blocks is implemented in Quartus II that includes a timer block, a pulse width modulation block, a PID controller block and a FIR-filter block. The system is used to control a power converter and the result is evaluated.

Thèse numérisée par la Direction des bibliothèques de l'Université de Montréal.

Master´s thesis deals with creating circuit for receiving data from industrial camera. IP Core is designing for FPGA. Theoretical part of the work describes SDI interface, analysis of relevant SMPTE standards and specification of data format. The thesis include general characteristics of multigigabit transceivers. Practical part include VHDL description of SDI receiver. Thesis presents simulations of created circuit, implementation for real application and measurement results for signal transmission over slip ring.

Ce travail de thèse traite de la caractérisation par Spectroscopie d'Impédance de l'impédance d'une pile à combustible en charge et plus particulièrement de l'évaluation de l'influence de l'humidité sur les performances de la pile. Après un état de l'art sur les différentes méthodes de caractérisation de l'impédance d'une pile et les différentes méthodes de mesure de l'humidité, la problématique est posée. Nous modélisons la pile Nexa de 47 cellules de type PEMFC, en intégrant des mesures expérimentales au niveau du modèle. Le modèle dynamique décrit en VHDL-AMS est un modèle au niveau macroscopique prenant en compte le côté électrique des différentes cellules constituant la pile. Ce modèle prend en compte la caractéristique des deux dernières cellules qui présentent un phénomène d'inondation remarqué lors des mesures expérimentales. Le système de purge de la Nexa est également pris en compte dans le code. L'étude expérimentale passe par la mise en place d'un banc de mesure pour la caractérisation de l'impédance de la pile Nexa par Spectroscopie d'Impédance, ainsi que la mesure de l'humidité en sortie de la pile. Les mesures d'impédances complexes corrélées à celles de l'humidité nous ont amenées à déterminer l'influence de l'humidité sur les performances de la pile. La concordance entre les résultats du modèle et ceux du banc de mesure, tant en DC que en AC, sont concluants. L'erreur constatée à l'issue de la comparaison entre les résultats théoriques et expérimentaux est inférieure à 1.5%. / This thesis deals with the characterization of the impedance of an on load fuel cell by Electrochemical Impedance Spectroscopy method and particularly the assessment of the humidity influence on the fuel cell performances. After a state of the art on different methods to characterize the impedance of a fuel cell and different methods of measuring humidity, the problem is posed. We model the PEM Nexa stack which consists of 47 cells, integrating experimental measurements. The dynamic model described in VHDL-AMS is a model at the macroscopic level, taking into account the electrical side of individual cells constituting the fuel cell. This model takes into account the characteristics of the last two cells exhibiting the phenomenon of flooding seen in experimental measurements. The purge system of the Nexa is also reflected in the code. The experimental study involves the establishment of a Testbench for characterizing the impedance of the Nexa fuel cell by Impedance spectroscopy method, and measuring the humidity at the output of the stack. The complex impedance measurements correlated with those of humidity led us to determine the influence of humidity on the performance of the fuel cell. The correlation between the model results and those of the Testbench, both in DC than in AC, are conclusive. The error in between theoretical and experimental results is less than 1.5%.

Publicación a texto completo no autorizada por el autor / Describe el desarrollo de un equipo electrónico prototipo utilizando dispositivos lógicos programables complejos (CPLD’s) que controla al sistema de recepción del radar del radio observatorio de Jicamarca (ROJ). Los CPLD’s han sido programados mediante el lenguaje de descripción de hardware VHDL, utilizando para la síntesis, simulación, implementación y programación de estos dispositivos el software de distribución gratuita QUARTUS II de ALTERA. Ha sido necesario la utilización de tres CPLD’s, programados para cumplir sus propias funciones y las complementarias con los otros, motivo por el cual ha sido necesario darles la capacidad de comunicarse entre ellos. Finalmente, el prototipo ha sido sometido a pruebas y ha demostrado ser de características superiores a otro desarrollado en el ROJ denominado REX-2X y es comparable y superior en algunas de sus características al equipo comercial ECHOTEK GC214, satisface las necesidades del ROJ y cumple con las exigencias del mercado, por lo que ha tenido aceptación en otras instituciones nacionales como la Marina de Guerra del Perú y otras entidades extranjeras que se dedican a la investigación de la ionósfera, contribuyendo de esta manera con el desarrollo de la tecnología nacional. / Tesis

O objetivo deste trabalho é propor a concepção de um Módulo de Interface utilizando dispositivos lógicos reconfiguráveis para executar comandos de monitoração e comutação de relés em módulos internos do foguete de sondagem. O Módulo de Interface foi elaborado de modo a permitir que o Banco de Controle comande remotamente os módulos da Rede Elétrica do veículo via comunicação serial. Este Módulo é de fundamental importância para implementação do novo Banco de Controle de Foguetes de Sondagem que substituirá os painéis de controle por um sistema computadorizado. Este sistema facilitará a reconfiguração do Banco de Controle para cada nova missão de lançamento, permitirá um melhor registro de eventos, possibilitará a geração de alertas em caso de anomalias ou de seqüências indevidas de comando e reduzirá o número de condutores do cabo umbilical. Para a concepção deste trabalho foram criados componentes escritos em VHDL (VHSIC Hardware Description Language) necessários para o funcionamento do Módulo de Interface. Estes componentes foram testados utilizando o dispositivo lógico programável "EPF10K20" da placa educacional "UP 1" da Altera. Neste trabalho também foram elaborados e testados os circuitos que realizam interface com o dispositivo lógico reconfigurável.