<p>The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channels should be sorted into 4 bit words with one bit taken successively from each of the channels. A requirement on the data transfer was that the data in the four channels should arrive synchronously to the FPGA. A Virtex-5 FPGA on a LT110X platform was used with <em>Rocket^TMIO</em> GPT transceivers tightly integrated with the FPGA logic. Since the actual DUT (Device Under Test) was not in place during the work, the transceivers of the FPGA were used for both sending and receiving data. The transmission was shown to be successful for both eight and ten bit data widths. At this stage a small skew between the data in the four channels was observed. This was solved by storing the information in separate memories, one for each of the channels, to make possible to later form the 4 bit words in the PC (MatLab). The memories were two port FIFOs writing in data at 240 MHz (10 bit data width) or 300 MHz (8 bit data width) and read out at 50 MHz.</p> / <p>Syftet med examensarbetet var att konfigurera en FPGA med höghastighetsportar så att data från en prototyp av en 4 bitars ΣΔ analog-till-digital omvandlare kan samlas in med en hastighet av 2.4 Gbps i var och en av fyra kanaler och att utveckla ett protokoll för överföring av dessa data från FPGAn till en PC för analys. Insamlade data ska sorteras i 4 bitars ord med en bit successivt tagen från var och en av kanalerna. Ett krav på dataöverföringen var att data i de fyra kanalerna skulle anlända synkront till FPGAn. En Virtex-5 FPGA på en LT110X plattfrom användes med <em></em>GTP transceivrar tätt integrerade med FPGA logiken. Då utrustningen som skulle testas inte var tillgänglig under tiden arbetet utfördes användes FPGAns transceivrar till att både sända och ta emot data. Överföring av data med både 8 och 10 bitars datavidd uppnåddes framgångsrikt. Data i de fyra kanalerna visade sig dock inte anlända synkront till mottagaren. Detta problem löstes genom att lagra informationen i separata minnen, ett för varje kanal, överföra data från minnena till PCn och där med hjälp av MatLab sortera dem till 4 bitars ord. Som minnen användes tvåportars FIFOn där data skrivs in med en hastighet av 240 MHz (10 bitars datavidd) eller 300 MHZ (8 bitars datavidd) och läses ut med en hastighet av 50 MHz.</p>

<p>Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time. A long list of ready to use functional blocks so called intellectual property (IP) blocks can be used in FPGAs. The latest FPGAs can also be bought with one or more embedded processors, in form of hard processor cores or as licenses for soft processor cores. This will speed up the design phase and of course also decrease the crucial time to market even more. </p><p>The purpose of this master’s thesis was to develop a waveform generator to generate a sine signal and a cosine signal, I and Q, used for radio/radar applications. The digital signals should have an output data rate of at least 100 MHz. The digital part of the system should be implemented in hardware using e.g. an FPGA. To convert the digital signals to analog signals two D/A converters are used. The analog signals, I and Q, should have a bandwidth of 1 MHz - 11 MHz. </p><p>The waveform generator was developed and implemented using a Virtex II FPGA from Xilinx. An embedded microprocessor within the FPGA, MicroBlaze, in form of a soft processor core was used to control the system. A user interface program running on the microprocessor was also developed. Testing of the whole system, both hardware and software, was done. The system is able to generate digital sine and cosine curves of an output data rate of 100 MHz.</p>

<p>Denna rapport behandlar konstruktion och tillverkning av ett videokort till Versa Module Eurocard (VME) bussen. Kortet skall användas vid laborationer i kurser där mikrodatorkort VM42 från PEP Modular Computer används. Grafikkortet klarar en upplösning på minst 640x480 punkter med 24-bitars färg. Hela konstruktionen är uppbyggd kring Lattice^® MACH4A3-384/160. Designen av MACH kretsen är uppbyggd i Very High speed integrated hardware Description Language (VHDL) med hjälp av programmen ActiveHDL, Synplify Pro^®, ispDesignExpert samt LatticePRO. </p> / <p>This report is about the construction and fabrication of a video card for the Versa Module Euro card (VME) bus. The card will be used as a platform in laborations in courses including the VM42 microcontroller from PEP Modular Computer. The card is able to display a resolution of at least 640x480 pixels with 24bit color. The heart in the construction is the Lattice^® MACH4A3-384/160 Complex Programmable Logic Device (CPLD). All programming is done in Very High speed integrated hardware Description Language (VHDL) with the help of ActiveHDL, Synplify Pro^®, ispDesignExpert and LatticePRO software tools.</p>

<p>This thesis is a part of a bigger project which goal is to make a DSP that is instruction compatible with the Motorola DSP56002. The goal of this part is to make a behavioural model with timing of the address generation unit in the DSP. </p><p>The AGU unit can handle 4 different types of arithmetic’s including linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles several ways of calculating addresses as post/pre increment/decrement by a number. It can address 3 different memories, where 2 new addresses can be calculated at the same time in different memories. </p><p>This model will be used as a golden model for the RTL model of the AGU that is one of the main parts in the DSP.</p>

<p>The development in electronics increases the demand for good design methods and design tools in the field of electrical engeneering. To improve their design methods Ericsson Microwave Systems AB is interested in using computer tools to create a link between the specification and the implementation of a digital system in a FPGA. </p><p>Xilinx System Generator for DSP is a tool for implementing a model of a digital signalprocessing algorithm in a Xilinx FPGA. To evaluate Xilinx System Generator two testcases has been designed. </p><p>The testcases are selected to represent the FPGA designs made at Ericsson Microwave Systems. The testcases show that Xilinx System Generator can be used to effectivly implement a model made in Simulink in a FPGA from Xilinx. The result of the implementation is comparable to the implementation of VHDL code written by hand. </p><p>The use of tools for implementation of a model in hardware cause change in the design methods used at Ericsson Microwave Systems. The higher level of abstraction introduced by System Generator results in the design decisions made at system level having a higher impact on the final realization.</p>

<p>The use of microcontrollers and FPGAs is getting more and more wide spread in electronic designs. A recent developmenthas been to implement microcontrollers onboard the FPGA, there are a lot of benefits but also disadvantages with this. Often the microcontroler requires a lot of resources in the expensive FPGA. This is where PicoBlaze, a microcontroller provided by Xilinx, fits in. It is designed with one main object, keep it as small and powerful as possible. </p><p>In this report PicoBlaze is evaluated and documented. Two implementations have been done. One smaller to show how to use PicoBlaze and one larger implementation of an Ethernet network interface. The function of the implementations have been verified on a experiment board utilizing a Virtex-II FPGA. </p><p>The conclusion is that PicoBlaze is a very powerful microcontroller in comparison to the resources it uses on the FPGA. It uses only a little more than 80 slices on a Virtex II FPGA. This is its main advantage, the disadvantages of PicoBlaze is its limited program memory and the limited address space.</p>

<p>Due to the development towards more dense programmable devices (FPGAs) it is today possible to fit a complete embedded system including microprocessor, bus architecture, memory, and custom peripherals onto one single reprogrammable chip, it is called a System-on-Chip (SoC). The custom peripherals can be of literally any nature from I/O interfaces to Ethernet Media Access Controllers. The latter core, however, usually consumes a big part of a good sized FPGA. The purpose of this thesis is to explore the possibilities of interfacing an FPGA based Microblaze system to an off-chip Ethernet MAC/PHY. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. This work includes evaluation of different available Ethernet devices, decision of interface technology, implementation of the interface, testing and verification. Since the ISA interface still is a common interface to Ethernet MAC devices a bus bridge is implemented linking the internal On-Chip Peripheral Bus (OPB) with the ISA bus. Due to delivery delays of the selected Ethernet chip a small on-chip ISA peripheral was constructed to provide a tool for the testing and verification of the bus bridge. The main result of this work is an OPB to ISA bus bridge core. The bridge was determined to work according to specification, and with this report at hand the connection of the Ethernet chip to the system should be quite straightforward.</p>

<p>In this thesis, we explore different algorithms for the inversion of Vandermonde matrices and the corresponding suitable architectures for implement in FPGA. The inversion of Vandermonde matrix is one of the three master projects of the topic, Implementation of a digital error correction algorithm for time-interleaved analog-to-digital converters. The project is divided into two major parts: algorithm comparison and optimization for inversion of Vandermonde matrix; architecture selection for implementation. A CORDIC algorithm for sine and cosine and Newton-Raphson based division are implemented as functional blocks.</p>

<p>Digital Radio Frequency Memory (DRFM) is a technique widely used by the defense industry in, for example, electronic countermeasure equipment for generating false radar targets. The purpose of the DRFM technique is to use high-speed sampling to digitally store and recreate radio frequency and microwave signals. At Saab Bofors Dynamics AB the technique is used, among others, in the Electronic Warfare Simulator (ELSI). The DRFM technique is implemented in a full-custom ASIC circuit that has been mounted on circuit boards in ELSI. Today, the progress in the programmable hardware field has made it possible to implement the DRFM design in a Field Programmable Gate Array (FPGA). The FPGA technology has many advantages over a full custom ASIC design.</p><p>Hence, the purpose of this master's thesis has been to develop a new DRFM design that can be implemented in an FPGA, using a hardware description language called VHDL. The method for this master's thesis has been to first establish a time plan and a requirement specification. After that, a design specification has been worked out based on the requirement specification. The two specifications have served as a basis for the development of the DRFM circuit. One of the requirements on the design was that the circuit should be able to communicate through an external Ethernet interface. A part of the work has, thus, been to review available external Ethernet modules on the market. The result is a DRFM design that has been tested through simulations. The tests shows that the design works as described in the design specification.</p>

<p>Detta examensarbete har som syfte att konstruera en prototyp av en testsändare inom Sbandet,2.2 – 2.4 GHz. Arbetet innefattar konstruktion och utveckling av hårdvara och kodför testsändaren, samt tester och optimering av den framtagna prototypen.Koden designades för en FPGA i Quartus II med VHDL. I FPGA:n hanteraskommunikationen mellan användaren och hårdvaran. Designen av mönsterkortet gjordes iprogrammet Altium Designer. Det resulterade i ett kretskort i glasfiber med två lager ochytmonterade komponenter som handlöddes. Huvudkretsarna i hårdvaran är en FPGA, enfrekvensmixer, en lokaloscillator och två olika förstärkare. Lokaloscillatorn genererarbärfrekvensen medans FPGA:n modulerar indata och omvandlar det till datafrekvenser.Mixern blandar bärfrekvensen med data via amplitudmodulering och ger ut en RF-signalsom förstärks innan den sänds ut.Resultatet efter optimering är att testsändaren genererar en ren bärfrekvens inomS-bandet och kompenserar väl för modulationsfel vid generering av RF-signalen. Denöverför data som vid test kan avläsas och valideras av en demoduleringsapparat förflygdata.</p>