Digital Radio Frequency Memory (DRFM) is a technique widely used by the defense industry in, for example, electronic countermeasure equipment for generating false radar targets. The purpose of the DRFM technique is to use high-speed sampling to digitally store and recreate radio frequency and microwave signals. At Saab Bofors Dynamics AB the technique is used, among others, in the Electronic Warfare Simulator (ELSI). The DRFM technique is implemented in a full-custom ASIC circuit that has been mounted on circuit boards in ELSI. Today, the progress in the programmable hardware field has made it possible to implement the DRFM design in a Field Programmable Gate Array (FPGA). The FPGA technology has many advantages over a full custom ASIC design. Hence, the purpose of this master's thesis has been to develop a new DRFM design that can be implemented in an FPGA, using a hardware description language called VHDL. The method for this master's thesis has been to first establish a time plan and a requirement specification. After that, a design specification has been worked out based on the requirement specification. The two specifications have served as a basis for the development of the DRFM circuit. One of the requirements on the design was that the circuit should be able to communicate through an external Ethernet interface. A part of the work has, thus, been to review available external Ethernet modules on the market. The result is a DRFM design that has been tested through simulations. The tests shows that the design works as described in the design specification.

I detta examensarbete har olika sätt att implementera färgrymdskonverterare i multipel konstant multiplikationsteknik beskrivits med VHDL, syntetiserats och jämförts med avseende på effektförbrukning.

The purpose of this thesis is to explore the formal verification technique of completion functions and equivalence checking by verifying two pipelined cryptographic circuits, KASUMI and WG ciphers. Most of current methods of communications either involve a personal computer or a mobile phone. To ensure that the information is exchanged in a secure manner, encryption circuits are used to transform the information into an unintelligible form. To be highly secure, this type of circuits is generally designed such that it is hard to analyze. Due to this fact, it becomes hard to locate a design error in the verification of cryptographic circuits. Therefore, cryptographic circuits pose significant challenges in the area of formal verification. Formal verification use mathematics to formulate correctness criteria of designs, to develop mathematical models of designs, and to verify designs against their correctness criteria. The results of this work can extend the existing collection of verification methods as well as benefiting the area of cryptography. In this thesis, we implemented the KASUMI cipher in VHDL, and we applied the optimization technique of pipelining to create three additional implementations of KASUMI. We verified the three pipelined implementations of KASUMI with completion functions and equivalence checking. During the verification of KASUMI, we developed a methodology to handle the completion functions efficiently based on VHDL generic parameters. We implemented the WG cipher in VHDL, and we applied the optimization techniques of pipelining and hardware re-use to create an optimized implementation of WG. We verified the optimized implementation of WG with completion functions and equivalence checking. During the verification of WG, we developed the methodology of ``skipping" that can decrease the number of verification obligations required to verify the correctness of a circuit. During the verification of WG, we developed a way of applying the completion functions approach such that it can deal with a circuit that has been optimized with hardware re-use.

In this thesis, a direct digital synthesis (DDS) based function generator design module is presented, defined and implemented using two digital hardware modeling/design languages namely SystemC and VHDL. The simulation, synthesis and applicability performances of these two design languages are compared by following all digital hardware design stages. The advantages and open issues of SystemC based hardware design flow are emphasized in order to be a reference for future studies. SystemC initially appeared as a modeling language like HDL design languages. In the last years, SystemC gained popularity also as a hardware design language and it is expected to become alternative to traditional design languages. Using a single platform for hardware modeling, design and verification reduces the spent time and cost. The designed DDS function generator module supports standard I2C and UART communication protocols and it is in ready to use format for digital applications. In this thesis, the function generator module VHDL code is implemented into Xilinx FPGA and verified on the hardware platforms.

In today&rsquo / s complex technological systems, there is a need of multi tasking several units running in accordance. Each unit is composed of several intelligent microcontroller cards. Each intelligent card performs a different task that the unit is responsible of. For this reason, there is a need of common communication bus between these cards in order to accomplish the task duties. VME (Versa Module Euro-Card) bus is a well known, the most reliable and the commonly used communication bus, even if it was standardized three decades ago. In this thesis work, the world wide accepted VME parallel bus protocol is implemented on FPGA (Field programmable Gate Array). The implementation covers the VME standard slave protocols. The VME Slave Module has been developed by VHDL (Very high level Hardware Description Language). The simulations have been carried over a computer based environment. After the verification of the VHDL code, an Intellectual Property (IP) core is synthesized and loaded into the FPGA. The FPGA based printed circuit board has been designed and the IP core&rsquo / s function has been tested by bus protocol checkers for all of its functionality. The designed hardware has several standard serial communication ports, such as / USB, UART and I2C. Through the developed card and the add-on units, it is also possible to communicate with these serial ports over the VME bus.

<p>Allting började med att jag fick i uppdrag av Euromaint Industry i Skövde att konstruera en alfanumerisk display i syfte att ersätta en utgången display som inte längre nytillverkas. Jag fick i uppdrag att välja ut en modern, lämplig grafisk display och bygga ett interface mellan den nya displayen och den industriella maskin som displayen skall sitta på. Efter att ha letat hos någraelektronikleverantörer kom jag fram till att en TFT-skärm från det japanska företaget Kyocera var den som passade bäst. Skärmen hade ett VGA-liknandeinterface och min uppgift blev att sätta mig in i hur VGA fungerar. Efter att ha konstaterat att det krävdes en snabbare krets än en microcontroller för att använda VGA, var det endast en programmerbar logikkrets, en FPGA, som gällde. Denna FPGA sköter nu ensam om såväl VGA-interfacet som inläsningen av informationen från den industriella NC-maskinen.</p> / <p>Everything started when I got a task from Euromaint Industry in Skövde, Sweden, to develop an alphanumerical display that could replace an old one, which was sold out. I got a task to choose a modern, suitable, graphical display and develop an interface between the new display and the industrial machine, which the old one was connected to. I have searched for a display at some suppliers of electronic components and I have found a TFT-display from the Japanese company Kyocera. The display had an interface similar to VGA so I had to study VGA to see how it works. Then I realized that I needed a faster circuit than a microcontroller. Then I chose a programmable logic circuit, an FPGA, to control the VGA-sweep. Today the FPGA-circuit controls the whole system.</p>

<p>In different applications, in digital domain, it is necessary to change the sampling rate by an arbitrary number. For example Software Radio which should handle different conversion factors and standards. </p><p>This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates. </p><p>The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost. The creating VHDL generator of Farrow-based structure to speed up the design process is the main task of this work. The suitable design technique which is the most important thing in any design work is presented in the report as well. </p><p>The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB. The source code is attached to the report. And some results from tests of the implemented scheme.</p>

<p>En del av en Audioanalystor har blivit utveckladoch implementerad som en applikation i det hårdvarubeskrivande språket VHDL. Denna del har sedan programmerats in i en PLD-krets på ett kretskort som används i audiotester för mobiltelefoner på Flextronics. Applikationen konverterar data så att det ska gå att skicka information mellan telefonen och olika mätinstrument. Applikationen består av två äldre applikationer. Av dessa två har en blivit helt implementerad. I den andra kvarstår att finna orsaken till varför den ger ifrån sig felaktigt data i form av oönskat brus. Arbetet avbröts p.g.a. slutdatum. A part of an audio analyzer has been developed and implemented as an application in the hardware description language VHDL. This part has later been programmed into a PLD device on a circuit board used for audio tests on mobile telephones at Flextronics. The application converts data, making it possible to send information between the telephone and different measuring instruments. The application consists of two older applications. One of them has been fully implemented. What is left in the other part is to find the cause why it is sending wrong data as unwanted noise. The work had to be stopped when deadline was reached</p> / <p>A part of an audio analyzer has been developed and implemented as an application in the hardware description language VHDL. This part has later been programmed into a PLD device on a circuit board used for audio tests on mobile telephones at Flextronics. The application converts data, making it possible to send information between the telephone and different measuring instruments. The application consists of two older applications. One of them has been fully implemented. What is left in the other part is to find the cause why it is sending wrong data as unwanted noise. The work had to be stopped when deadline was reached.</p>

<p>This thesis is investigating the new globally asynchronous locally synchronous (GALS) technology for integrated circuits. Different types of asynchronous wrappers are tested and a new wrapper design is presented. It also investigates the possibility to use VHDL for asynchronous simulation and synthesis. The conclusions are that the GALS technology is possible to use but that it needs new synthesis tools, because todays tools are designed for synchronous technology.</p>

<p>In this thesis a number of energy saving methods for a multiplier on algorithmic level are investigated. For the investigation a multiplier is constructed in VHDL, after which the circuit's performance is investigated. A number of techniques for reduced power consumption are introduced in the circuit and are then evaluated. The conclusions are that all investigated methods, pipelining, interleaving and voltage scaling, should be maximally made use of in order to minimize the power consumption.</p> / <p>I detta arbete undersöks ettantal energibesparande metoder för en multiplikator på algoritmnivå. För undersökningen konstrueras en multiplikator i VHDL, varefter kretsens prestanda undersöks. Ett antal tekniker för minskad effektförbrukning införs i kretsen och utvärderas därefter. Slutsatsen är att samtliga undersökta metoder, pipelining, interleaving och spänningsskalning, bör utnyttjas maximalt för att minimera effektförbrukningen. </p>