331 |
Hardware implementation of a synchronization state buffer in VHDLBarton, Jonathan L. January 2008 (has links)
Thesis (M.E.E.)--University of Delaware, 2008. / Principal faculty advisor: Guang R. Gao, Dept. of Electrical and Computer Engineering. Includes bibliographical references.
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332 |
Design and simulation of a primitive RISC architecture using VHDL /Moustakas, Evangelos. January 1991 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1991. / Spine title: Design of a RISC using VHDL. Typescript. Includes bibliographical references (leaf 71).
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333 |
Simulation of a morphological image processor using VHDL. mathematical components /Chen, Wei-chun. January 1993 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references (leaf 96).
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334 |
Simulation of a morphological image processor using VHDL. control mechanism /Chen, Hao. January 1993 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references (leaf 101).
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335 |
Timing distribution in VHDL behavioral models /Gadagkar, Ashish, January 1992 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 97-100). Also available via the Internet.
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336 |
Contribution aux méthodes d'implantation matérielle des protocoles de communication /Wytrebowicz, Jacek. January 1996 (has links)
Th. doct.--Informatique et réseaux--Paris--ENST, 1995. / Bibliogr. p. 115-125. Résumé en français et en anglais.
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337 |
Effiziente Methoden zur netzwerkbasierten Modellbeschreibung für die EMV-Simulation im Automobilbereich /Frank, Florian. January 2008 (has links)
Zugl.: Erlangen, Nürnberg, Universiẗat, Diss., 2008.
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338 |
Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer /Guthrie, Thomas G. January 2005 (has links) (PDF)
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2005. / Thesis Advisor(s): Douglas J. Fouts. Includes bibliographical references (p. 61). Also available online.
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339 |
Design of a hardware efficient key generation algorithm with a VHDL implementation /Goeke, James A. January 1993 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references.
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340 |
VHDL modeling and synthesis of the JPEG-XR inverse transform /Frandina, Peter. January 2009 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 2009. / Typescript. Includes bibliographical references (leaf 45).
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