Diplomová práce se zabývá návrhem termální kamery pro biologické aplikace. V první části je popsáné infračervené záření, také známé jako thermální záření. Pokračuje popisem emisivity objektů, která hraje důležitou roli při stanovení teploty snímaného objektu. Dále je v první kapitole uveden přehled typů termálních detektorů a jejich základní vlastnosti. Druhá kapitola stručně seznamuje se zákládními hardwarovými komponenty vyvíjené kamery. V poslední kapitole je popsán celý proces vývoje softwaru. Ten zahrnuje vývoj IP jader, kernel modulů a C++ knihoven.

This paper describes implementation of the whole cryptographic protocol TLS including control logic and used cryptographic systems. The goal is to implement an application in the FPGA technology, so it could be used in hardware accelerated network card. The reason for this is new supported higher transmission speeds that Ethernet is able to operate on, and the absence of implementation of this protocol on FPGA. In the first half of this paper is described theory of cryptography followed by description of TLS protocol, its development, structure and operating workflow. The second half describes the implementation on the chosen technology that is also described here. It is used already existing solutions of given cryptographic systems for the implementation, or at least their parts that are modified if needed for TLS. It was implemented just several parts of whole protocol, such are RSA, Diffie-Hellman, SHA and part of AES. Based on these implementations and continuing studying in this matter it was made conclusion, that FPGA technology is inappropriate for implementation of TLS protocol and its control logic. Recommendation was also made to use FPGA only for making calculations of given cryptographic systems that are controlled by control logic from software implemented on standard processors.

Tato práce je zaměřena na zpracování a analýzu USB komunikačního protokolu a implementace jeho jednotlivých částí do FPGA obvodu s využitím programovacího jazyka VHDL. Ve finální podobě by měla práce představovat souhrnný a ucelený dokument popisující principy USB rozhraní a jeho komunikace doplněných praktickým návrhem v jazyce VHDL, který by byl schopen převést data do USB.

The master's thesis briefly analyses the principle of OFDM modulation, possibilities of the synchronization and channel estimation in OFDM. The simply model of OFDM system is made in MATLAB. Because of the implementation in FPGA is generated the behavioral description of the OFDM demodulator through the combination of the schematics description and the description in the VHDL language. The ISE development environment is used.

Aim of this Diploma thesis was to create a device capable of receiving navigational data from GPS. These data are subsequently stored in fixed memory and after connection with the PC are displayed it on the satellite map. The device was realized by using FPGA and GPS module LEA-5s. Description was created in the VHDL language, which was implemented into the circuit. The part of VHDL design was description of PICOBLAZE processor that controls whole system. For displaying and archiving data stored in device was created PC application GPS TRACER. It is able to display stored trace on the satellite map by using Google maps server. For created device were designed and manufactured PCBs, which were manually fitted.

This project deals with implementation of a first order Sigma–Delta AD converter on the FPGA. This ADC is design for an audio signal processing. ADC is build up partially from digital blocks implemented in FPGA (programmed using VHDL) and from few analog components placed external to FPGA. Output from ADC is PCM signal. Data from ADC is created UDP datagram, which is sent to PC via network connection. Income data are received in created program, which save data to text file. This text file is processing in MATLAB.

The scope of this work is to map both conventional and less conventional methods of signal detection in the radio channel, computer simulation of selected methods and subsequent implementation selected method (algorithm) to FPGA chip.

This thesis deals with designing and realisation of a bus analyzer. The analyzer is programmed into Spartan-3AN XC3S50AN programmable logic device. The design includes a SRAM parallel memory and a graphical LCD display. Data output is realized through USB, microSD memory card and VGA. The thesis also describes the use of a software microprocessor PicoBlaze for the control of the LCD display and user interface. The last part deals with a test application using an 8-bit microcontroller connected to an alphanumeric display and a discussion over the results.

In the text of the master´s thesis, it is at first briefly referred about Energetic Material Measurement topic in general. Emphasis is placed especially at the description of the Velocity of Detonation and short analysis of selected measurement method. The most significant part of the paper is dedicated to the design and description of the system that was created in ISE Design Suite environment using VHDL language. The development was performed with respect to oncoming integration into the board with FPGA and A/D converters. The operation of detection algorithm which was created based on the MATLAB model was verified in the final part of the thesis by simulation of processing of real optical probe signals.

This diploma thesis is about design of a 2D graphics controller for FPGA circuits. It consists of two parts. In the first phase, it analyses 2D acceleration and interface for communication with display devices of the operation system Linux. The second part contains design of graphics controller itself and its implementation. Part of the thesis is description of components that the controller consists of and evaluation of resultant implementation. For testing purposes on selected FPGA circuit, test modules adding support for used peripherals and test data generation are created.