Filtering is an important part of digital processing, since the applications often require a change of features of a digital or analog signal. A digital filter is a device or a system that removes or alters certain parts of a signal. Optical fibers are used to transmit information over longer distances and at higher bandwidths than traditional copper cables. In order to enable high-rate transmission in optical communication systems, it is necessary to have a filter that compensates for chromatic dispersion in optic links, since the dispersion alters the signal in an unwanted way. This thesis presents the implementation and evaluation of two filter architectures, used in fiber-optic communication. The clock frequency of the implemented designs reaches 475 MHz, which results in a processing speed of 60 GS/s.

The Keccak Sponge Function is the winner of the National Institute of Standards and Technology (NIST) competition to develop the Secure Hash Algorithm-3 Standard (SHA-3). Prior work has developed reference implementations of the algorithm and described the structures necessary to harden the algorithm against power analysis attacks which can weaken the cryptographic properties of the hash algorithm. This work demonstrates the architectural changes to the reference implementation necessary to achieve the theoretical side channel-resistant structures, compare their efficiency and performance characteristics after synthesis and place-and-route when implementing them on Field Programmable Gate Arrays (FPGAs), publish the resulting implementations under the Massachusetts Institute of Technology (MIT) open source license, and show that the resulting implementations demonstrably harden the sponge function against power analysis attacks.

Different network devices require processing of the network traffic. To process the network traffic, it is necessary to parse headers of particular protocols packed in incoming ethernet frames. The processed headers can be repackaged to ethernet frames and sent back to the network. The goal of this thesis is to design and implement a circuit for analysis and parsing of ethernet frames, together with circuit for deparsing ethernet frames. The circuits are designed for throughputs of up to 400 Gb/s. The circuits are implemented for the FPGA technology.

The thesis deals with design and implementation of controllers for the RMAP protocol, which is used by SpaceWire network endpoints to access memory contents of another endpoint. The theoretical research introduces concepts of the SpaceWire network, then describes the RMAP protocol and the AMBA AHB bus interface in detail. The practical part of this thesis then uses this information to design and implement controllers for the RMAP protocol. It first defines an architecture of these controllers, then describes design of individual blocks based on this architecture. As a next step, the thesis describes methods used to verify designed controllers and to test these controllers in an FPGA chip. Finally, an analysis of maximum frequency and usage of FPGA resources is done based on estimates provided by the synthesis tool.

This thesis deals with network substandards from the TSN group (IEEE 802.1Q), which deal with prioritization of network traffic in TSN networks. These sub-standards include 802.1QBV and 802.1QBU, which have been described in more detail and compared in terms of network permeability and latency. Substandard 802.1QBU was chosen for the design implementation in FPGA. The design was described in VHDL. The designed design was verified by simulations, using self-tests. The work includes synthesis and time analysis.

This thesis deals with network substandards from the TSN group (IEEE 802.1Q), which deal with prioritization of network traffic in TSN networks. These sub-standards include 802.1QBV and 802.1QBU, which have been described in more detail and compared in terms of network permeability and latency. Substandard 802.1QBU was chosen for the design implementation in FPGA. The design was described in VHDL. The devloped design was verified by simulations, using self-tests. The work includes synthesis and time analysis.

This diploma thesis is about using vector control (or field-oriented control) of synchronous BLDC and PMSM motors on FPGAs. First part describes basic theory of these motors and how to control them. Then vector control is detailed and its parts as (or Clarke) and Park transformation. Rest of the thesis deals with the design of universal controller with adjustable accuracy in VHDL language. Data is separated from computing part which utilizes custom arithmetic-logic unit. In the last part of the thesis the design is tested in simulator using model of PMSM motor.

This thesis deals with innovation of tasks from bachelor subject Logical systems. Three tasks in total in VHDL language were designed and tested for development kit Digilent Nexys 3 and peripheries Pmod which are connected to it. First task is focused on reading pressed key on matrix keyboard. Second and third tasks targets on displaying pressed key on OLED display, they differ by used controller for this display. Instructions for all tasks were created.

Master thesis is dealing with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In theoretical part of thesis are explained different types of mechanism used for providing quality of service in communication networks. Furthermore the brief description o VHDL, FPGA and framework Netcope Development Kit is a piece of theoretical part as well. The outcome of practical part contains a design, limiting packet queues based on Tocken Bucket mechanism. Design verification was made by simulations, synthesis and real implementation on smart NIC NFB-200G2QL. All kind of verificaion results are summerized in last three chapters.

The aim of this thesis is to analyze various kinds of co-simulation techniques and to design integration these techniques into Lissom simulation platform. The first section of this thesis shows capabilities of external interfaces of simulation platforms for HDL languages VHDL, Verilog and SystemVerilog and of tool Matlab. The second section deals with design of synchronization mechanism among Lissom simulation platform and others simulation platforms using mentioned external interfaces. In the last part the testing of implemented solutions and evaluation of results is described.