Die Simulation heterogener Systeme auf hoher Abstraktionsebene gewinnt auf Grund der zunehmenden Komplexität technischer Systeme stetig an Bedeutung. Unter heterogenen Systemen versteht man technische Systeme, die aus analoger und digitaler Elektronik, aus Komponenten verschiedener physikalischer Domänen wie mechanischen Strukturen, thermischen und optischen Komponenten sowie aus Software bestehen können. Genügte es bisher, die einzelnen Komponenten für sich in ihrer eigenen Domäne mit einem speziellen Simulator zu simulieren, so ist es heute unerläßlich, auch die Interaktionen zwischen den Komponenten zu erfassen. Um solche Systeme mit einer einheitlichen Beschreibungsform erfassen zu können, entstand aus der digitalen Hardwarebeschreibungssprache VHDL die Systembeschreibungssprache VHDL-AMS. Bei der Modellierung eines Systems muß das tatsächliche Verhalten der Komponenten abstrahiert werden, um mathematisch erfaßbar und in begrenzter Zeit simulierbar zu sein. Der Grad der Abstraktion beeinflußt jedoch die Genauigkeit der Simulationsergebnisse wesentlich. Dabei muß bzw. kann das Verhalten in unterschiedlichen Komponenten unterschiedlich stark abstrahiert werden, um noch akzeptable Simulationsgenauigkeiten erzielen zu können. VHDL-AMS erlaubt die Beschreibung von Komponenten auf unterschiedlichen Abstraktionsniveaus. Man kann die unterschiedlich abstrakten Modelle der Komponenten aber nur schwer in einer Systemsimulation gemeinsam simulieren, da unterschiedlich abstrakte Modelle auch unterschiedlich abstrakte Schnittstellen aufweisen, so daß die Modelle nur mühsam miteinander verbunden werden können. Ein Austausch eines abstrakten Modells einer Komponente gegen ein weniger abstraktes Modell oder umgekehrt ist mit vielen fehleranfälligen und zeitaufwendigen Anpassungsschritten verbunden. Im Rahmen dieser Arbeit wird ein methodischer Ansatz vorgestellt, der es auf der Basis einer Vereinheitlichung der Modellschnittstellen ermöglicht, unterschiedlich abstrakte Modelle gemeinsam zu simulieren und einzelne Modelle gegen abstraktere oder weniger abstrakte Modelle ohne nennenswerten Zeit- und Modellierungsaufwand auszutauschen. Es werden die zu verwendenden Interfaceobjekte und Datentypen für digitale, analoge elektrische und nichtelektrische Schnittstellen unter VHDL-AMS und SystemC-AMS vorgestellt. Ebenso werden Methoden vorgestellt, die digitales, ereignisdiskretes Verhalten auf konservative elektrische Schnittstellen bzw. nichtkonservatives analoges Verhalten auf digitale Schnittstellen abbilden. Weiterhin wird erläutert, wie sich digitale Protokolle über Abstraktionsebenen hinweg übertragen lassen und ein modifizierter Top-Down Design-Flow vorgestellt. Die Demonstration der Anwendbarkeit der Methode erfolgt anhand eines Beispiels.

Thèse de doctorat--Électronique et communications--Paris--ENST, 2006. / Bibliogr. p. 157-166. En annexe articles en anglais.

Thèse de doctorat : Microélectronique : Strasbourg 1 : 2007. / Titre provenant de l'écran-titre. Notes bibliogr.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990. / Thesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.

Thesis (Ph.D.), Memorial University of Newfoundland, 2000. / Bibliography: leaves 155-165.

During this research, the concepts of Systems Engineering were applied to embedded system design. The objective was to apply the Systems Engineering methodology to the design of a particular embedded system. A Video Surveillancesystem was chosen as the particular embedded system. Systems Engineering concepts provide the foundation for an optimized design process and for the coordination between system modules. The functionality of the Video Surveillance system was achieved through the partitioning of the overall system functionality into three separate modules. The three modules were Image Capture, Image Processing and Image Transmission. The methodology employed resulted in a system that was flexible and portable. The three modules were designed using their own set of specifications and with completely defined linking interfaces. Following a concrete set of specifications resulted in a system, which can be modified at any later stage without the necessity of changing the whole architecture. The Video Surveillance system fulfilled the overall system requirements as well as those imposed by the subsystems. The partitioning of functionality resulted in ease of implementation and better upgradeability. Design based on Systems Engineering concepts provides for ease of integration. In addition, for modules that follow the same protocol, the existence of well defined interfaces enables connectivity to a variety of external units.

Αντικείμενο της παρούσας μεταπτυχιακής εργασίας είναι ο σχεδιασμός και η ανάπτυξη συστήματος κατανεμημένης διαμοιραζόμενης μνήμης ως τμήμα της αρχιτεκτονικής πολυεπεξεργαστικού συστήματος SiScape. Λόγω των ιδιαιτεροτήτων της αρχιτεκτονικής αυτής, το σύστημα μνήμης της και συγκεκριμένα η κρυφή μνήμη δευτέρου επιπέδου που καθιστά δυνατή τη λειτουργία του, κρίθηκε απαραίτητο να σχεδιαστεί και να αναπτυχθεί από το μηδέν, προκειμένου να ανταποκριθεί στις απαιτήσεις της. Ο σχεδιασμός της κρυφής μνήμης δευτέρου επιπέδου περιγράφηκε στη γλώσσα περιγραφής υλικού VHDL. / The purpose of this master thesis is the design and development of a shared distributed memory system as part of the multiprocessor architecture SiScape. Because of the architecture's irregular structure, it was imperative that the memory system and particularly the second level cache that enables its functionality, was designed from scratch, to fill all of its requirements. The design of the second level cache was described using the VHDL hardware description language.

The School of Electrical, Electronic and Computer Engineering of the North-West University is conducting research about RFID (radio frequency identification) medium range reader systems for an international company, iPico. The focus area of the present research is the development of a robust tag detection algorithm for noisy environments. During the past three years a digital detection algorithm was developed. This digital detection algorithm delivered significant improvements in detection of RFIDs over its analogue counterpart, especially in noisy environments. However, the digital detection algorithm was found to be very sensitive with regard to data rate deviations. Although the latter algorithm improved the detection of RFIDs, ghost (absent) tags were now also detected. The objectives of this project are, to develop an enhanced detection algorithm which is less sensitive to frequency deviations and to eliminate the appearance of the so called ghost tags. The proposed enhanced algorithm will be implemented on a FPGA (field programmable gate array), more specific the Altera Cyclone EP1CT144C6 FPGA. / Thesis (M.Ing. (Computer and Electronical Engineering))--North-West University, Potchefstroom Campus, 2009.

The School of Electrical, Electronic and Computer Engineering of the North-West University is conducting research about RFID (radio frequency identification) medium range reader systems for an international company, iPico. The focus area of the present research is the development of a robust tag detection algorithm for noisy environments. During the past three years a digital detection algorithm was developed. This digital detection algorithm delivered significant improvements in detection of RFIDs over its analogue counterpart, especially in noisy environments. However, the digital detection algorithm was found to be very sensitive with regard to data rate deviations. Although the latter algorithm improved the detection of RFIDs, ghost (absent) tags were now also detected. The objectives of this project are, to develop an enhanced detection algorithm which is less sensitive to frequency deviations and to eliminate the appearance of the so called ghost tags. The proposed enhanced algorithm will be implemented on a FPGA (field programmable gate array), more specific the Altera Cyclone EP1CT144C6 FPGA. / Thesis (M.Ing. (Computer and Electronical Engineering))--North-West University, Potchefstroom Campus, 2009.

ABSTRACT A DEPENDABLE COMPUTING APPLICATION G&uuml / ng&ouml / r, Ugur M.S., Department of Electric and Electronics Engineering Supervisor : Prof. Dr. Hasan Cengiz G&uuml / ran April 2005, 129 pages This thesis focuses on fault tolerance which is kind of dependable computing implementation. It deals with the advantages of fault tolerance techniques on Single Event Upsets (SEU) occurred in a Field Programmable Gate Array (FPGA). Two fault tolerant methods are applied to floating point multiplier. Most common SEU mitigation method is Triple Modular Redundancy (TMR). So, two fault tolerance methods, which use TMR, are tested. There are three printed circuit boards (PCBs) and one user interface software in the setup. By user interface software running on a computer, user can inject fault or faults to the selected part of the system, which uses TMR with voting circuit or TMRVC TMR with voting and correction circuits on floating point multiplier. After inserting fault or faults, user can watch results of the fault injection test by user interface software. One of these printed circuit boards is called as a Test Pattern Generator. It is responsible for communication between the Fault Tolerant Systems and the user interface software running on a computer. Fault Tolerant Systems is second PCB in the setup. It is used to implement fault tolerant methods on fifteen bits floating point multiplier in the FPGA. First one of these methods is TMR with voter circuit (TMRV) and second one is TMR with voter and correction circuits (TMRVC). Last PCB in the setup is Display PCB. This PCB displays fault tolerant test result and floating point multiplication result. All the functions on Test Pattern Generator and Fault Tolerant Systems are implemented through the use of a Field Programmable Gate Array (FPGA), which is programmed using the Very High Speed IC Description Language (VHDL). Implementation results of the used methods in FPGA are evaluated to observe the performance of applied methods for tolerating SEU.