The initial goal of this report was to implement and compare cosine modulated filter banks. Because of time limitations, focus shifted towards the implementation. Filter banks and multirate systems are important in a vast range of signal processing systems. When implementing a design, there are several considerations to be taken into account. Some examples are word length, number systems and type of components. The filter banks were implemented using a custom made software, especially designed to generate configurable gate level code. The generated code was then synthesized and the results were compared. Some of the results were a bit curious. For example, considerable effort was put into implementing graph multipliers, as these were expected to be smaller and faster than their CSDC (Canonic Signed Digit Code) counterparts. However, with one exception, they turned out to generate larger designs. Another conclusion drawn is that the choice of FPGA is important. There are several things left to investigate, though. For example, a more thorough comparison between CSDC and graph multipliers should be carried out, and other DCT (Discrete Cosine Transform) implementations should be investigated.

This thesis work contains a litterature study about electrical motors in general and how PWM-patterns for brushless DC-motors can be made. A suitable method has been implemented as a simulation model in VHDL. A simulation model of a brushless DC-motor which describes the phasecurrents, torque and angular velocity has also been made. The motor model made simulations easier for the complete PWM-system. The design was synthesised and tested with a prototypeboard including a SPARTAN II FPGA. In order to test the design, a powerstage and a motor was included. The tests showed that the design was working as expected according to the previous simulations. A study about an alternative way to control a brushless DC-motor has also been made. This alternative is best suited when the generated back-EMK for the motor is sinusoidal. A simulation model for a part of a system like this has been made, and it has been synthesised in order to examine if it is possible to implement using a FPGA availible today.

Implementering av FIR filter kan göras på olika sätt. I detta examensarbete har två olika varianter beskrivits med hjälp av VHDL, syntetiserats, simulerats och sedan jämförts med avseende på effektförbrukning.

This thesis describes the VHDL behavioral model design of a DSP On Chip Emulation Unit. The prototype of this design is the OnCE port of the Motorola DSP56002. Capabilities of this On Chip Emulation Unit are accessible through four pins, which allows the user to step through a program, to set the breakpoint that stop program execution at a specific address, and to examine the contents of registers, memory, and pipeline information. The detailed design that includes input/output signals and sub blocks is presented in this thesis. The user will interact with the DSP through a GUI on the host computer via the RS232 port. An interface between the RS232 and On Chip Emulation Unit is therefore designed as well. The functionality is designed to be same as described by Motorola and it is verified by a test bench. The writing of the test bench, test sequence and results is presented also.

Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time. A long list of ready to use functional blocks so called intellectual property (IP) blocks can be used in FPGAs. The latest FPGAs can also be bought with one or more embedded processors, in form of hard processor cores or as licenses for soft processor cores. This will speed up the design phase and of course also decrease the crucial time to market even more. The purpose of this master’s thesis was to develop a waveform generator to generate a sine signal and a cosine signal, I and Q, used for radio/radar applications. The digital signals should have an output data rate of at least 100 MHz. The digital part of the system should be implemented in hardware using e.g. an FPGA. To convert the digital signals to analog signals two D/A converters are used. The analog signals, I and Q, should have a bandwidth of 1 MHz - 11 MHz. The waveform generator was developed and implemented using a Virtex II FPGA from Xilinx. An embedded microprocessor within the FPGA, MicroBlaze, in form of a soft processor core was used to control the system. A user interface program running on the microprocessor was also developed. Testing of the whole system, both hardware and software, was done. The system is able to generate digital sine and cosine curves of an output data rate of 100 MHz.

This thesis is a part of a bigger project which goal is to make a DSP that is instruction compatible with the Motorola DSP56002. The goal of this part is to make a behavioural model with timing of the address generation unit in the DSP. The AGU unit can handle 4 different types of arithmetic’s including linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles several ways of calculating addresses as post/pre increment/decrement by a number. It can address 3 different memories, where 2 new addresses can be calculated at the same time in different memories. This model will be used as a golden model for the RTL model of the AGU that is one of the main parts in the DSP.

The development in electronics increases the demand for good design methods and design tools in the field of electrical engeneering. To improve their design methods Ericsson Microwave Systems AB is interested in using computer tools to create a link between the specification and the implementation of a digital system in a FPGA. Xilinx System Generator for DSP is a tool for implementing a model of a digital signalprocessing algorithm in a Xilinx FPGA. To evaluate Xilinx System Generator two testcases has been designed. The testcases are selected to represent the FPGA designs made at Ericsson Microwave Systems. The testcases show that Xilinx System Generator can be used to effectivly implement a model made in Simulink in a FPGA from Xilinx. The result of the implementation is comparable to the implementation of VHDL code written by hand. The use of tools for implementation of a model in hardware cause change in the design methods used at Ericsson Microwave Systems. The higher level of abstraction introduced by System Generator results in the design decisions made at system level having a higher impact on the final realization.

The use of microcontrollers and FPGAs is getting more and more wide spread in electronic designs. A recent developmenthas been to implement microcontrollers onboard the FPGA, there are a lot of benefits but also disadvantages with this. Often the microcontroler requires a lot of resources in the expensive FPGA. This is where PicoBlaze, a microcontroller provided by Xilinx, fits in. It is designed with one main object, keep it as small and powerful as possible. In this report PicoBlaze is evaluated and documented. Two implementations have been done. One smaller to show how to use PicoBlaze and one larger implementation of an Ethernet network interface. The function of the implementations have been verified on a experiment board utilizing a Virtex-II FPGA. The conclusion is that PicoBlaze is a very powerful microcontroller in comparison to the resources it uses on the FPGA. It uses only a little more than 80 slices on a Virtex II FPGA. This is its main advantage, the disadvantages of PicoBlaze is its limited program memory and the limited address space.

In different applications, in digital domain, it is necessary to change the sampling rate by an arbitrary number. For example Software Radio which should handle different conversion factors and standards. This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates. The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost. The creating VHDL generator of Farrow-based structure to speed up the design process is the main task of this work. The suitable design technique which is the most important thing in any design work is presented in the report as well. The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB. The source code is attached to the report. And some results from tests of the implemented scheme.

In this thesis, we explore different algorithms for the inversion of Vandermonde matrices and the corresponding suitable architectures for implement in FPGA. The inversion of Vandermonde matrix is one of the three master projects of the topic, Implementation of a digital error correction algorithm for time-interleaved analog-to-digital converters. The project is divided into two major parts: algorithm comparison and optimization for inversion of Vandermonde matrix; architecture selection for implementation. A CORDIC algorithm for sine and cosine and Newton-Raphson based division are implemented as functional blocks.