Techn. Univ., Diss., 2001--Darmstadt

Στα πλαίσια αυτής της διπλωματικής εργασίας μελετήσαμε τους Secure Hash Algorithms, σχεδιάσαμε μια υλοποίηση αυτών με Reconfigurable αρχιτεκτονική και το συνθέσαμε σε ένα FPGA board. Η εργασία ξεκίνησε με μελέτη των προτύπων του SHA-160/224/256/384/512 και ιδιαίτερα των μαθηματικών συναρτήσεων υπολογισμού και των χαρακτηριστικών μεγεθών του κάθε αλγόριθμου. Επικεντρωθήκαμε στην εύρεση των κοινών σημείων και στα χαρακτηριστικά μεγέθη και στις συναρτήσεις και στο πως θα μπορούσαμε να εκμεταλλευτούμε αυτά για να πετύχουμε μια υλοποίηση και των πέντε αλγορίθμων χωρίς να γίνονται περιττοί υπολογισμοί και επαναχρησιμοποίηση area. Η υλοποίηση μας θα έπρεπε επίσης να έχεις τέσσερα μπλοκ διαφορετικών μηνυμάτων ταυτόχρονα προς επεξεργασία χωρίζοντας την σε τέσσερα ανεξάρτητα στάδια με pipeline τεχνική για την βελτίωση της απόδοσης. Επίσης κάθε μήνυμα μπορεί να χρησιμοποιεί οποιοδήποτε από τους αλγόριθμους SHA-160/224/256/384/512. Εφόσον η αρχική υλοποίηση μας πιστοποιήθηκε ότι παράγει το σωστό αποτέλεσμα σύμφωνα με τα test vector των προτύπων χρησιμοποιήσαμε την τεχνική του partial unrolling operations για να μειώσουμε τα απαιτούμε clock για τον υπολογισμό των hash τιμών των μηνυμάτων. Τέλος, με την χρήση Modelsim και Precision Physical, υλοποιήσαμε και συνθέσαμε και τις δυο αρχιτεκτονικές μας συγκρίνοντας τα αποτελέσματα και προτείνοντας μελλοντικές βελτιώσεις και προσθήκες στο σύστημά μας. / In this thesis we studied the Secure Hash Algorithms, designed a Reconfiguble Implementation of them and synthesized it on an FPGA board. The work started with the study of the SHA-160/224/256/384/512 prototypes and especially with the mathematical equations and the algorithm sizes. We focused on finding the common points between the algorithm sizes and the mathematical equations along with how we could take advantage of them so we could achieve an implementation of the five SHA algorithms without doing any not necessary computations and area reuse. The implementation must, also, have four different blog messages at the same time for computation in the processor unit, leading to a pipeline distinction of four autonomous parts and improved performance. Moreover the message chooses the algorithm that will be used for encryption. After we validated the original reconfigurable architecture by using the test vectors of the prototypes, we used the partial unrolling of operations technique to decrease the needed number of clocks for the computation of the message digest. Finally, by using Modelsim and Precision Physical we implemented and synthesized both proposed architectures, compared the results and proposed future improvements and additions in our system.

Η παρούσα ειδική ερευνητική εργασία εκπονήθηκε στα πλαίσια του Διατμηματικού Προγράμματος Μεταπτυχιακών Σπουδών Ειδίκευσης στην “Ηλεκτρονική και Επεξεργασία της Πληροφορίας” στο Τμήμα Φυσικής του Πανεπιστημίου Πατρών. Αντικείμενο της παρούσας εργασίας είναι η σχεδίαση και ανάπτυξη ενός βασικού μικροϋπολογιστικού συστήματος με τη χρήση της VHDL και FPGAs. Το σύστημα βασίζεται σε μία επαυξημένη, σε δυνατότητες, εκδοχή της σχετικά απλής cpu του Carpinelli και ενσωματώνει τη δυνατότητα παράλληλης διασύνδεσης μίας σειράς περιφερειακών διατάξεων και υποκυκλωμάτων. Στο πρώτο κεφάλαιο παρουσιάζεται πλήρως η σχεδίαση ενός τέτοιου συστήματος και μελετάται η δομή των επιμέρους δομικών στοιχείων που το απαρτίζουν. Στο δεύτερο κεφάλαιο παρουσιάζεται η περιγραφή του μικροϋπολογιστικού συστήματος σε γλώσσα VHDL και η πλήρης εξομοίωσή του με τη βοήθεια του λογισμικού Quartus v7.2 της ALTERA. Στο τελευταίο κεφάλαιο παρουσιάζεται η υλοποίηση του μικροϋπολογιστικού συστήματος στην αναπτυξιακή πλατφόρμα DE2 της εταιρείας ALTERA. / This project objective is the design and development of an FPGA based microcomputer system in VHDL. The system is based on an enhanced version of Carpinelli’s relative simple cpu and is implemented with parallel input and output ports and interrupts. The first chapter presents the full design of such a system and study the structure of the individual components that compose it. The second chapter presents the implementation of the microcomputer system in VHDL and the simulation results using Quartus v7.2 software suite. The last chapter presents the implementation of the system in a FPGA using DE2 development board of ALTERA.

Ο σκοπός της παρούσας Διπλωματικής Εργασίας είναι η μελέτη και η υλοποίηση ενός 8085 προσομοιωτή σε FPGAs με τη χρήση VHDL. H υλοποίηση έγινε με την βοήθεια του περιβάλλοντος εξομοίωσης του Quartus v7.2 της ALTERA, με την χρήση της γλώσσας VHDL [8],[10].Η εργασία αυτή χωρίζεται σε 12 κεφάλαια: Στο πρώτο κεφάλαιο γίνεται αναφορά στο μικροεπεξεργαστή και στα τεχνικά του γνωρίσματα [1], [2], [4]. Στο δεύτερο κεφάλαιο γίνεται μια εκτενής αναφορά στη γλώσσα VHDL [3], [10]. Στο τρίτο κεφάλαιο παρουσιάζεται η αναπτυξιακή πλατφόρμα DE2 της εταιρίας ALTERA. Παρουσιάζονται αναλυτικά οι δυνατότητες και τα σχεδιαστικά χαρακτηριστικά της αναπτυξιακής κάρτας DE2 της ALTERA καθώς και τεχνική απεικόνισης video με τη χρήση FPGA [3], [9], [14]. Στο τέταρτο κεφάλαιο αναλύεται η λειτουργία του πρώτου μεγάλου τμήματος του μικροεπεξεργαστή, της ALU. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [6], [12], [13]. Στο πέμπτο κεφάλαιο αναλύεται η λειτουργία του register file. Πρόκειται για το τμήμα των καταχωρητών, το οποίο είναι υπεύθυνο για την μεταφορά δεδομένων και την λειτουργία των διαύλων διευθύνσεων. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [11], [13], [14]. Στο έκτο κεφάλαιο αναλύεται η λειτουργία του τμήματος ελέγχου διακοπών. Πρόκειται για το τμήμα το οποίο εξυπηρετεί οποιαδήποτε αίτηση για διακοπή και το οποίο έχει οριστεί να είναι υπεύθυνο και για την σειριακή επικοινωνία. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [1], [12], [13]. Στο έβδομο κεφάλαιο γίνεται μια πρώτη απόπειρα σύνδεσης των τριών πρώτων μεγάλων τμημάτων του μικροεπεξεργαστή [12], [13]. Στο όγδοο κεφάλαιο αναλύεται η λειτουργία της control unit ως μονάδα ελέγχου και διαχείρισης των σημάτων ελέγχου του όλου κυκλώματος του μικροεπεξεργαστή. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [12], [13]. Στο ένατο κεφάλαιο παρουσιάζεται το κύκλωμα του μικροεπεξεργαστή μέσα από την σύνδεση των επιμέρους τμημάτων του. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [7], [12], [13]. Στο δέκατο κεφάλαιο παρουσιάζεται ο μικροπρογραμματισμός της microprogram ROM της control unit. Αναλύεται διεξοδικά η λειτουργία των σημάτων ελέγχου των τμημάτων του μικροεπεξεργαστή για την εκτέλεση κάθε μιας εντολής του 8085 [7], [12], [13]. Στο ενδέκατο κεφάλαιο γίνεται εξομοίωση ορισμένων προγραμμάτων για τον έλεγχο της ορθής λειτουργίας των εντολών και των σημάτων ελέγχου και εξόδου του μικροεπεξεργαστή 8085 [1], [12], [13]. Στο δωδέκατο κεφάλαιο παρουσιάζεται η υλοποίηση του μικροεπεξεργαστή στην αναπτυξιακή πλατφόρμα DE2 της εταιρείας ALTERA [3], [14]. Τελειώνοντας θα ήθελα να ευχαριστήσω τον επιβλέποντα της προσπάθειας αυτής Αναπληρωτή Καθηγητή κ. Ευάγγελο Ζυγούρη, η καθοδήγηση του οποίου υπήρξε καθοριστική. / The purpose of this thesis is the design of an 8085 emulator in FPGAs using VHDL. The implementation was done with the simulation environment of ALTERA Quartus v7.2, using VHDL. The project is divided into 12 chapters: The first chapter refers to the 8085 microprocessor and it’s technical features [1], [2], [4]. The second chapter is a detailed presentation of the VHDL language [3], [10]. The third chapter presents DE2 development board of Altera. Capabilities and design features of DE2 board are presented and vga video display generation using FPGAs is explained [3], [9], [14]. The fourth chapter analyzes the operation of the first large section of the microprocessor, ALU. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [6], [12], [13]. The fifth chapter presents the operation of the register file. Register File is responsible for data transfer and operation of the address bus. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [11], [13], [14]. The sixth chapter presents microprocessor 's interrupts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [1], [12], [13]. The seventh chapter is a first attempt to link the first three major sections of the microprocessor [12], [13]. The eighth chapter presents the operation of the control unit. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [12], [13]. The ninth chapter presents the circuit of the microprocessor through the connection of all individual parts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [7], [12], [13]. The tenth chapter presents the microprogramming of microprogram ROM of the control unit. It analyzes in detail the operation of the control signals of the parts of the microprocessor to perform each of 8085 command [7], [12], [13]. The eleventh chapter presents the simulation of microprocessor through assembly programs written in RAM memory of 8085 microprocessor [1], [12], [13]. The twelfth chapter presents the implementation of microprocessor in FPGAs using DE2 development board of Altera [3], [14].

Resumo: A aplicabilidade da rede de comunicação junto com o avanço tecnológico é constantemente explorada pelos projetistas de automação e controle, pois, estas vertentes podem melhorar o desempenho de um processo industrial. O padrão IEEE 1451, surge em meio a estes desafios, com intuito de homologar conceitos e tecnologias para implementar uma rede de transdutores inteligentes. Neste trabalho desenvolveu-se uma plataforma de hardware/software para ser utilizada na automação industrial, tanto cabeamento como sem fio, de acordo com os padrões IEEE 1451.2 e IEEE 1451.5. Essa plataforma, denominada neste trabalho por plataforma IEEE 1451, é composta por um hardware, o Módulo de Interface para Transdutores (TIM - Transducer Interface Module), e por um software Processador de Aplicação para Rede de Comunicação (NCAP - Network Capable Application Processor). A lógica de controle e as especificações dos transdutores (TEDS - Transducer Electronics Data Sheet) foram inseridas no TIM por meio da programação (linguagem C/C++) do processador NIOS II e o hardware sintetizado em FPGA da família Cyclone II, especificamente na placa de desenvolvimento DE2 da Altera Corporation. A programação do processador NIOS II baseou-se em um template definido neste trabalho como IEEE 1451 que possui funções e bibliotecas específicas para atender às funcionalidades das aplicações e das normas IEEE 1451. O NCAP possui características de um software supervisório e foi desenvolvido com tecnologia Java no ambiente NetBeans IDE (Integrated Development Environment) versão 6.5. Entre as principais funções deste NCAP está a capacidade de enviar e receber os dados através da porta RS232, geração de relatório incluindo a TEDS, interface gráfica dinâmica e identificação de usuários. A plataforma IEEE 1451 foi testada... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: Designers usually exploit the fast evolution of technology along with the application of communication networks to improve the performance on industrial processes. The IEEE 1451 standard comes to aid in the development of networks of intelligent transducers, by defining concepts and technologies used in their implementations. This works intends to provide an application consisting of a hardware/software platform to be used in industrial automation, either wireless or not, according to the 1451.2 and 1451.5 IEEE standards. This IEEE 1451 platform is composed by a hardware part, the Transducer Interface Module (TIM), and a software part, the Network Capable Application Processor (NCAP). The control logic and the transducer specifications (TEDS - Transducer Electronics Data Sheet) were inserted in the TIM by programming in C/C++ a NIOS II processor, synthesized in a FPGA of the Cyclone II family, using the DE2 development board from Altera Corporation. The NIOS II programming was based on an IEEE 1451 template, with functions and libraries to implement the functionalities of the IEEE 1451 applications and guidelines. The NCAP software resembles a supervisory system and was developed in Java in the NetBeans integrated development environment, version 6.5. Amongst its main functions are the capabilities of report generation including TEDS, a dynamic graphical interface, user identification and the ability to send and receive data through a RS232 port. This IEEE 1451 platform was tested in the automation of different applications, demonstrating its flexibility and rapid prototyping suited for the development of control systems. Other advantages are the use of an object oriented language in the development of the NCAP software, which facilitates the code reuse, and the use of reconfigurable hardware for the TIM implementation. The results from this work showed that the technology applied... (Complete abstract click electronic access below) / Orientador: Alexandre César Rodrigues da Silva / Coorientador: Aparecido Augusto de Carvalho / Banca: Dionizio Paschoareli Junior / Banca: Luis Carlos Origa de Oliveira / Banca: Eduardo do Valle Simões / Banca: Mauro Conti Pereira / Doutor

Submitted by Lara Oliveira (lara@ufersa.edu.br) on 2017-09-11T22:44:19Z No. of bitstreams: 1 AllysonALF_DISSERT.pdf: 2286744 bytes, checksum: 6ff716a2c28bcb7db9ac2c2775cefd83 (MD5) / Approved for entry into archive by Vanessa Christiane (referencia@ufersa.edu.br) on 2017-10-27T13:04:28Z (GMT) No. of bitstreams: 1 AllysonALF_DISSERT.pdf: 2286744 bytes, checksum: 6ff716a2c28bcb7db9ac2c2775cefd83 (MD5) / Approved for entry into archive by Vanessa Christiane (referencia@ufersa.edu.br) on 2017-10-27T13:07:44Z (GMT) No. of bitstreams: 1 AllysonALF_DISSERT.pdf: 2286744 bytes, checksum: 6ff716a2c28bcb7db9ac2c2775cefd83 (MD5) / Made available in DSpace on 2017-10-27T13:10:30Z (GMT). No. of bitstreams: 1 AllysonALF_DISSERT.pdf: 2286744 bytes, checksum: 6ff716a2c28bcb7db9ac2c2775cefd83 (MD5) Previous issue date: 2017-08-25 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Along with the need to develop controllers for industrial processes, it arises the need to study advanced control techniques, such as fuzzy controllers, that can supply nonlinearities inherent in the systems. The implementation of these fuzzy controllers based on Hardware Description Language (HDL) has the advantage of high speed and fast reprogramming for use in another project, by changing only desired variables. The objective of this study is to develop a fuzzy controller implemented in VHDL (Very High Speed Integrated Circuit Hardware Description Language) for a tank level system and to evaluate its effectiveness, comparing it with a fuzzy controller developed in Matlab®. Its methodology is to develop a fuzzy system described in VHDL and divided into coding, inference and decoding for a Quanser cylindrical tank system and another system with a trapezoidal format tank. The results of this proposal were satisfactory given the limitations presented by the system / Com a necessidade de desenvolver controladores para processos industriais, surge a necessidade de estudar técnicas de controle avançado, como por exemplo, controladores fuzzy, que possam suprir não linearidades inerentes nos sistemas. A implementação destes controladores fuzzy baseados em Linguagem de Descrição de Hardware (HDL) tem como vantagem a alta velocidade e a reprogramação rápida para utilização em outro projeto, alterando apenas variáveis desejadas. O objetivo do trabalho é desenvolver um controlador fuzzy implementado em VHDL (Very High Speed Integrated Circuit Hardware Description Language) para um sistema de nível de tanques e avaliar sua eficácia, comparando-o com um controlador fuzzy desenvolvido em Matlab®. Sua metodologia consiste em desenvolver um sistema fuzzy descrito em VHDL e divididos em codificação, inferência e decodificação para um sistema de tanque cilíndrico da Quanser e outro sistema com tanque de formato trapezoidal. Os resultados desta proposta se mostraram satisfatórios diante de limitações apresentadas pelo sistema / 2017-09-11

Este trabalho apresenta um sistema de Síntese de Alto Nível — geração automática de uma descrição estrutural no nível RT a partir de uma descrição comportamental algorítmica [MCF 88] —, abordando as tarefas de compilação para representação interna, transformações comportamentais, escalonamento, alocação, mapeamento e gera.são do controle. Sua principal contribuição esta na fase de transformações comportamentais, através da qual é possível explorar globalmente o paralelismo existente na descried° do sistema digital e, de maneira sistemática, pesquisar o espaço de projeto, ou seja, as possíveis implementações para o sistema digital, identificando a que melhor satisfaz as restrições especificadas pelo projetista. A Linguagem de Descried° de Hardware (HDL) usada no sistema de síntese é VHDL que oferece recursos para se descrever comportamento e estrutura, e se especificar restrições de projeto, alem de ter sido adotada como padrão pela IEEE. Parte-se da descried° algorítmica em VHDL comportamental do sistema digital. Tal descrição é compilada para uma representação interna baseada em grafos: cada bloco básico — seqüência de operações sem desvio — e representado por um Grafo de Fluxo de Dados (GFD); a transferência de controle entre blocos básicos — desvios condicionais e incondicionais — é representada pelo Grafo de Fluxo de Controle (GFC); e as relações de hierarquia — entidade, arquitetura, processos, subprogramas — são representadas pelo Grafo de Entidade (GE). O sistema de transformações é tal que a escolha e a ordem da aplicação das transformações possíveis (agrupa blocos consecutivos, agrupa ramos de if, desenrola laços) sobre um GFC gera uma Arvore — a Arvore de Transformações — cujos nodos folha representam os GFD's iniciais e os nodos internos os GFD's obtidos pela transformação aplicada sobre os seus nodos filhos. Construída a Arvore de Transformações, realiza-se um caminhamento em pós-ordem, determinando-se a melhor implementação possível para cada nodo da Arvore de Transformações. Por melhor implementação entenda-se a que, no mínimo, satisfaça as restrições de tempo ou de recursos especificadas pelo projetista. Para cada implementação, obtida usando-se algoritmos de escalonamento, alocação e mapeamento existentes, calcula-se um custo em fungi° dos recursos — unidades funcionais, registradores, interconexões — e do tempo — passos de controle — necessários implementação. Feito isso, caminha-se em pré-ordem pela árvore de Transformações comparando-se o custo da implementação do nodo pai com os custos de implementação dos seus nodos filhos: se o custo dos nodos filhos a maior que o do nodo pai, este é selecionado e seus nodos filhos não são visitados; caso contrario, a transformações que o gerou é descartada e visita-se os nodos filhos. Os nodos selecionados fardo parte da implementação final. O modelo de hardware utilizado adota a divisão clássica de sistema digital em Parte Operativa e Parte de Controle, como apresentada em [DAV 83]. Na implementação do prot6tipo do sistema de síntese escolheu-se, para o escalonamento e a alocação, o algoritmo Force-directed que possui complexidade linear — 0(n2 ) no pior caso — e tem mostrado bons resultados em comparação com os demais existentes [PAU 89]. Para o mapeamento de registradores adotou-se o algoritmo do programa REAL [KUR 87] também de complexidade linear; o mapeamento de unidades funcionais e interconexões baseia-se em [PAN 87]. 0 controlador a obtido diretamente do GFC final: cada nodo representa um estado e as arestas representam as transições entre estados. 0 protótipo foi aplicado a vários exemplos, relatados na literatura, mostrando resultados comparáveis. Aplicando-se o protótipo sobre exemplos com fluxo de controle mais complexo, verifica-se a eficiência do sistema de transformações na exploração do espaço de projeto. / High Level Synthesis is the automatic generation of a structural description of a circuit at the RT level from a behavioral description at the algorithm level [MCF 88]. In this work, a High Level Synthesis System which deals with the tasks of compilation to internal representation, behavioral transformations, scheduling, allocation, mapping and control generation is presented. Its main contribution is the behavioral transformation process. It makes possible the exploration of the global parallelism in the behavioral description and, systematically, to search the design space in order to find the structure that best fits the resource and timing constraints specified by the designer. The Hardware Description Language (HDL) used in the synthesis system is VHDL, HDL standardized by IEEE, which offers facilities for the behavior description, structure description and for the specification of design constraints. The input to the synthesis system is a behavioral algorithmic VHDL description of the digital system under design. This description is translated to an internal representation based on graphs: each basic block (sequence of operations without branches) is represented by a Data Flow Graph (DFG); the transfer of control between basic blocks (conditional and inconditional branches) is represented by a Control Flow Graph (CFG); the hierarchy of description (entity, architectural body, processes, subprograms) is represented by the Entity Graph (EG). The set of behavioral transformations is such that the selection and sequence of applicable transformations (Merge Consecutive Blocks, Merge If Branches, Unroll Loops, etc.) to a CFG can be represented by a tree, called Transformations Tree. In the Transformations Tree, the leaf nodes represent the initial DFGs and the internal nodes represent the DFGs obtained by the transformations applied on its son nodes. After the Transformation Tree has been generated, a transversal post-order is used to determine the best possible implementation for each node of the Transformations Tree. The best possible implementation is the one that, at least, satisfy the timing and resources constraints specified by the designer. A cost is determined in terms of the timing (control steps) and resources (functional units, registers, interconections, etc.) required by each implementation, which is produced using traditional algorithms for scheduling and allocation. Once the implementation for each node is done, a transversal pre-order is used to compare the implementation cost of a node, with the implementation costs of its son nodes: if the cost of its son nodes is greater, the father node is selected and its son nodes are not visited; otherwise the transformation that produced the father node is discarded, and the son nodes are visited. The selected nodes will be in the final implementation. The hardware model used in the synthesis system adopts the classical division of the digital system in a Data-Path and a Controller, such as presented in [DAV 83]. In the implementation of the synthesis system prototype, the Force-Directed algorithm [PAU 89] was adopted for scheduling and allocation, which has linear complexity — in the worst case 0(n2 ) — and produces good results when compared with other algorithms [PAU 91]. The algorithm of the REAL program [KUR 87] was used for the mapping of registers, which also has linear complexity. The mapping of functional units and interconections uses the ideas from [PAN 87]. The controller is directly obtained from the final GFC: each node represents a state and the transitions between states are represented by the edges. The prototype of the synthesis system, which is implemented in C, on SUN workstations, was applied to various examples of the literature and has showed comparable results. When applied to examples with more complex control flow, the efficiency of the set of behavioral transformations in the design space exploration can be verified.

Os sistemas eletrônicos digitais estão sendo cada vez mais utilizados em aplicações de telecomunicações, processamento de voz, instrumentação, biomedicina e multimídia. A maioria dessas aplicações requer algum tipo de processamento de sinal, sendo que essa função normalmente é executada em grande parte por um bloco digital. Além disso, considerando-se os diversos tipos de circuitos existentes num sistema, tais como memórias RAM (Random Access Memory) e ROM (Read Only Memory), partes operativas e partes de controle complexas, é cada vez mais importante a preocupação com o teste desses sistemas complexos. O aumento da complexidade dos circuitos a serem testados exige também um aumento na complexidade dos circuitos testadores (teste externo), tornando estes últimos muito caros. Uma alternativa viável é integrar algumas ou todas as funções de teste no próprio chip a ser testado. Por outro lado, essa estratégia pode resultar em um custo proibitivo em termos de área em silício.É interessante observar, no entanto, que se os testes e a função de processamento de sinal não necessitarem ser executados em paralelo, então é possível utilizar uma única área reconfigurável para realizar essas funções de uma maneira sequencial. Logo, este trabalho propõe uma arquitetura reconfigurável otimizada para a implementação desses dois tipos de circuitos (processamento digital de sinais e teste). Com esta abordagem pretende-se ter ganhos de área em relação tanto a uma implementação dedicada (full-custom) quanto a uma implementação em dispositivos reconfiguráveis comerciais. Para validar essas idéias, a arquitetura proposta é descrita em uma linguagem de descrição de hardware, e são mapeados e simulados algoritmos de teste e de processamento de sinais nessa arquitetura. S˜ao feitas estimativas da área ocupada pelas três abordagens (dedicada, dispositivo reconfigurável comercial e nova arquitetura proposta), bem como uma análise comparativa entre as mesmas. Também são feitas estimativas de atraso e frequência máxima de operação. / Digital electronic systems have been increasingly used in a large spectrum of applications, such as communication, voice processing, instrumentation, biomedicine, and multimedia. Most of these applications require some kind of signal processing. Most of this task is usually performed by a digital block. Moreover, these complex systems are composed of different kinds of circuits, such as RAM (Random Access Memory) and ROM (Read Only Memory) memories, complex datapaths and control parts. This way, the test of such systems is ever more important. Likewise, the increasingly complexity of the circuits to be tested requires more complex testers (external test), making the latter more expensive. An approach to address this problem is to embbed the test functions onto the chip to be tested itself. Nevertheless, this approach may bring a prohibitive cost in terms of area on silicon. However, if the test and the signal processing functions are not required to run in parallel, then it is possible to use the same reconfigurable area to implement these functions one after another. Thus, this work proposes an optimized reconfigurable architecture to implement this kind of circuits (digital signal processing and test). This approach intends to decrease the occupied area in comparison to a dedicated and also to a comercial reconfigurable device implementation. To validate these ideas, the proposed architecture is described using a hardware description language and some test and digital signal processing applications are mapped and simulated on this architecture. In this work an estimative of the occupied area by the three approaches (dedicated, comercial reconfigurable device, and the new proposed architecture) as well as a comparison analysis between them are performed. Likewise, a delay estimate is performed and the maximum operation frequency is evaluated.

Made available in DSpace on 2015-09-17T15:26:38Z (GMT). No. of bitstreams: 0 Previous issue date: 2015-06-16. Added 1 bitstream(s) on 2015-09-17T15:45:24Z : No. of bitstreams: 1 000846541.pdf: 17370024 bytes, checksum: 9ed1e29f49181dc8fe384db35c4fd1e4 (MD5) / Esta tese de doutorado se baseia na necessidade atual e tendência mundial da busca por tornar mais inteligentes os sistemas de distribuição de energia elétrica, por isso, o objetivo geral deste trabalho é desenvolver uma Arquitetura de Simulação em Tempo Real e Controle (ASTR&C) para alimentadores elétricos de distribuição, com o intuito de analisar a qualidade da energia e melhorar as ações de controle nos sistemas de distribuição, procurando assim aumentar a confiabilidade e sustentabilidade do sistema de potência. A ASTR&C utiliza uma plataforma VHDL-AMS como interface gráfica do usuário (Graphical user interface - GUI) para desenvolver a simulação do sistema elétrico e a linguagem VHDL (Very High Speed Integrated Circuit Description Language) para o desenvolvimento do sistema de gerenciamento e controle da rede de distribuição (Distribution Management System and Control - DMS&C), através de um dispositivo FPGA (Field Programmable Gate Array). Ambas as linguagens de descrição de hardware VHDL e VHDL-AMS (VHDL analog and mixed-signal), juntamente com as informações do sistema elétrico de distribuição, tornam possível a simulação em tempo real e controle de alimentadores de distribuição de energia elétrica. A GUI na plataforma VHDL-AMS, além de executar a simulação do sistema elétrico de distribuição, envolve dois processos: 1) Importação de todos os parâmetros do sistema de distribuição real, a partir de um arquivo de texto, possibilitando a alteração de quaisquer dados deste alimentador de distribuição em ambiente VHDL-AMS e 2) Envio dos dados de controle necessários para o dispositivo FPGA. O DMS&C desenvolvido está focado no gerenciamento do perfil de tensão do alimentador admitido como estudo de caso, realizado através de um dispositivo FPGA, o qual dispõe como prioridade o controle do regulador de tensão do sistema de distribuição, com base na comutação de TAP do mesmo. Neste... / This doctoral thesis is based on current need and global trend in the search for making smarter electric power distribution systems. For this reason, the objective of this work is to develop a Real-Time Simulation and Control (RTSC) architecture of electrical distribution feeders, in order to analyze power quality and improve the control actions in distribution systems, to increase power system reliability, and sustainability. The RTSC architecture uses VHDL-AMS platform as graphical user interface (GUI) to develop the simulation of the electrical system and VHDL (Very High Speed Integrated Circuit Description Language) language for developing the Distribution Management System and Control (DMS&C) through a FPGA device. Both VHDL and VHDL-AMS (VHDL analog and mixed-signal) hardware description languages along with electric distribution system information make possible the real-time simulation and control for electrical distribution feeders. The GUI in VHDL-AMS platform, which, besides running the simulation of the electrical distribution system, involves two processes: 1) Import of all parameters of the distribution system from a text file, making it possible to change any data of this distribution feeder into a VHDL-AMS environment, and 2) Sending necessary control data to the FPGA device. The developed DMS&C is focused on voltage profile management of admitted feeder as a case study, performed through a FPGA device, which provides as priority control of the distribution system voltage regulator, based on the voltage regulator TAP switching. In this context, DMS&C was developed to propose feeder voltage level regulation actions to the distribution system real controller, considering the real feeder characteristics, with concentrated loads and network reduction, for constituting the case study of this thesis. It stands out as the main contribution of this thesis work, the presentation of a novel real-time simulation and control ...

Os sistemas eletrônicos digitais estão sendo cada vez mais utilizados em aplicações de telecomunicações, processamento de voz, instrumentação, biomedicina e multimídia. A maioria dessas aplicações requer algum tipo de processamento de sinal, sendo que essa função normalmente é executada em grande parte por um bloco digital. Além disso, considerando-se os diversos tipos de circuitos existentes num sistema, tais como memórias RAM (Random Access Memory) e ROM (Read Only Memory), partes operativas e partes de controle complexas, é cada vez mais importante a preocupação com o teste desses sistemas complexos. O aumento da complexidade dos circuitos a serem testados exige também um aumento na complexidade dos circuitos testadores (teste externo), tornando estes últimos muito caros. Uma alternativa viável é integrar algumas ou todas as funções de teste no próprio chip a ser testado. Por outro lado, essa estratégia pode resultar em um custo proibitivo em termos de área em silício.É interessante observar, no entanto, que se os testes e a função de processamento de sinal não necessitarem ser executados em paralelo, então é possível utilizar uma única área reconfigurável para realizar essas funções de uma maneira sequencial. Logo, este trabalho propõe uma arquitetura reconfigurável otimizada para a implementação desses dois tipos de circuitos (processamento digital de sinais e teste). Com esta abordagem pretende-se ter ganhos de área em relação tanto a uma implementação dedicada (full-custom) quanto a uma implementação em dispositivos reconfiguráveis comerciais. Para validar essas idéias, a arquitetura proposta é descrita em uma linguagem de descrição de hardware, e são mapeados e simulados algoritmos de teste e de processamento de sinais nessa arquitetura. S˜ao feitas estimativas da área ocupada pelas três abordagens (dedicada, dispositivo reconfigurável comercial e nova arquitetura proposta), bem como uma análise comparativa entre as mesmas. Também são feitas estimativas de atraso e frequência máxima de operação. / Digital electronic systems have been increasingly used in a large spectrum of applications, such as communication, voice processing, instrumentation, biomedicine, and multimedia. Most of these applications require some kind of signal processing. Most of this task is usually performed by a digital block. Moreover, these complex systems are composed of different kinds of circuits, such as RAM (Random Access Memory) and ROM (Read Only Memory) memories, complex datapaths and control parts. This way, the test of such systems is ever more important. Likewise, the increasingly complexity of the circuits to be tested requires more complex testers (external test), making the latter more expensive. An approach to address this problem is to embbed the test functions onto the chip to be tested itself. Nevertheless, this approach may bring a prohibitive cost in terms of area on silicon. However, if the test and the signal processing functions are not required to run in parallel, then it is possible to use the same reconfigurable area to implement these functions one after another. Thus, this work proposes an optimized reconfigurable architecture to implement this kind of circuits (digital signal processing and test). This approach intends to decrease the occupied area in comparison to a dedicated and also to a comercial reconfigurable device implementation. To validate these ideas, the proposed architecture is described using a hardware description language and some test and digital signal processing applications are mapped and simulated on this architecture. In this work an estimative of the occupied area by the three approaches (dedicated, comercial reconfigurable device, and the new proposed architecture) as well as a comparison analysis between them are performed. Likewise, a delay estimate is performed and the maximum operation frequency is evaluated.