This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.

The purpose of this thesis is to introduce a reader with existed commercial applications and control the FITkit using QDevKit. The main goal of the thesis is proposed and implemeted modul for application QDevKit which makes easy proposal and progress applications for platform FITkit.

This thesis describes the requirements analysis, design and implementation of stateful packet filtering to an existing stateless firewall. They also deals with testing of the implemented system. The first two chapters describe the properties NetCOPE development platform for FPGA. They also describes the principle of operation           firewall, which also serves as a requirements specification for stateful firewall. Then describes the detailed design of individual modules to modify the existing firewall and the proposal for the creation of new modules. It also discusses the implementation of the proposed modules and testing for proper operation. Finally, it discuss the current state of the thesis and describes possible future expansion.

This masters thesis deals with design of the component facilitating communication between PCI bus and user component. Designed component is simplifying the communication protocol between designed and user components, while advanced functions of PCI bus are preserved. Target platform is COMBO6-PTM card containing FPGA with Spartan 3 technology. Communication with PCI bus is mediated by PLX component. Thesis also contains design of simplified communication protocol.

The goal of this project was to study pipelined processor architectures along with instruction and data cache. Chosen pipelined architecture should be designed and implemented using VHDL language. Firstly, I decided to implement the subscalar architecture first, secondly, three versions of scalar architecture. For these architectures synthesis into FPGA was done and performance of these architectures was compared on chosen algorithm. In the next part of this thesis I designed and implemented instruction and data cache logic for both architectures. However I was not able to synthetise these caches. Last chapter of this thesis deals with the superscalar architecture, which is the architecture of nowadays.

Genetic information of all living organisms is stored in DNA. Exploring of its structure and function represents an important area of research in modern biology. One of the interesting structures occurring in DNA are palindromes. Based on the research they are expected to play an important role in interpreting the information stored in DNA, because they are often observed near important genes. Palindromes searching is complicated by the presence of mutations (changes in sequences of DNA elements), which increases the time complexity of algorithms. Therefore it is reasonable to study their parallelization and acceleration. The objective of this work is a study of palindromes searching methods and acceleration architecture design. The hardware unit implemented in a chip with FPGA technology placed on ml555 board can speed up the calculation up to 6 667 times in comparison with the best-known software method relying on suffix arrays.

Tato diplomová práce pojednává o zmírnění bitové chybovosti bezkabelového optického spoje s užitím principu reciprocity aplikovaného na komunikační kanál, spolu s možností kódování přenášených dat. V této práci je implementováno LDPC a Reed-Solomonovo kódování pro jejich vyhovující vlastnosti. Zbytková rámcová chybovost je vypočtena a k dispozici jako výstup systému, který je implementovaný v hradlovém poli (FPGA).

Tato práce se zabývá návrhem výkonového měniče určeného pro použití ve fotovoltaických systémech. Klíčovým je použití programovatelného hradlového pole (FPGA) pro realizaci řídicích funkcí. Do detailu jsou diskutovány aspekty návrhu spínaných měničů a na základě takto získaných poznatků je zkonstruován funkční vzorek měniče.

Die vorliegende Arbeit beschreibt die Optimierung des VHBC-Compilers, die Erweiterung der Eingabedateiformate des Compilers um EDIF-Netzlisten, seine Anpassung an die veränderte Architektur der VHM und die Realisierung dieser Architektur mittels VHDL. Es wird der Aufbau und die Arbeitsweise des VHBC-Compilers erläutert und die neue Architektur der VHM ausführlich beschrieben. Dem geht ein Vergleich mit bestehenden Ansätzen rekonfigurierbarer Hardware und eine Analyse der Schwachpunkte der bestehenden VHM und des VHBC-Compilers voraus. / This work describes the optimization of the VHBC-compiler, its extension to the input format EDIF, its adjustment to the changed architecture of the VHM and the realization of the VHM by means of VHDL.

Es wurden verschieden Kodierungsarten fuer FSMs untersucht, schwerpunktmaessig Gray Code und andere Arten der hazardfreien Kodierung. Ein spezieller Kodierungsalgorithmus zur hazardfreien Kodierung wurde entwickelt und in eine Entwurfsumgebung implementiert. Ein weitere Schwerpunkt der Arbeit sind Codegeneratoren, die eine Verhaltensbeschreibung der FSM in Verilog oder in VHDL erzeugen.