This research consists of the design of a low-power, low-cost, nanosatellite computer system solution. The proposed system solution, and design and implementation of a multiple-bus master FPGA and health monitoring space computer subsystem are described. In the fall of 1998, the US Air Force (USAF) funded Virginia Polytechnic Institute & State University (Virginia Tech), The University of Washington (UW), and Utah State University (USU) with $100,000 each to pursue a formation-flying satellite cluster. The program specified that a cluster of three satellites would maintain radio contact through UHF cross-link communication to report relative positions, obtained through GPS, and coordinate scientific measurement mission activities. This satellite cluster, named Ionospheric Observation Nanosatellite Formation (ION-F) is presently scheduled for launch in June of 2003. Maintaining some degree of system reliability in the error-prone space environment was desired for this low-cost space program. By utilizing high-reliability components in key system locations, and monitoring less reliable portions of the computer system for faults, an improvement in overall system reliability was achieved. The development of a one-wire health monitoring bus master was performed. A Synchronous Serial Peripheral Interface (SPI) bus master was utilized to extend the communication capabilities of the CPU. In addition, discrete I/O functions and A/D converter interfaces were developed for system health monitoring and the spacecraft Attitude Determination and Control System (ADCS). / Master of Science

Configurable computing machines (CCMs) are available as plug in cards for standard workstations. CCMs make it possible to achieve computing feats on workstations that were previously only possible with super computers. However, it is difficult to create applications for CCMs. The development environment is fragmented and complex. Compilers for CCMS are emerging but they are in their infancy and are inefficient. The difficulties of implementing run time reconfiguration (RTR) on CCMs are addressed in this thesis. Tools and techniques are introduced to simplify the development and synthesis of applications and partitions for RTR applications. A multiplexed memory port (MMP) is presented in JHDL and VHDL that simplifies the memory interface, eases the task of writing applications and creating partitions, and makes applications platform independent. The MMP is incorporated into an existing CCM compiler. It is shown that the MMP can increase the compiler's functionality and efficiency. / Master of Science

À l'ère de systèmes électroniques intégrés, les ingénieurs font face au défi de concevoir et de tester des systèmes hétérogènes contenant des parties analogiques, numériques, mécaniques et même du logiciel embarqué. Cela reste très difficile car il n'y a pas d'outil unifiant ces différents domaines de l’ingénierie. Ces systèmes, dits hétérogènes, ont leur comportement exprimées et spécifiés par plusieurs formalismes, chacun particulier à son domaine d'expertise (diagramme de machines à état pour les circuits de contrôle numérique, équations différentielles pour les modèles mécaniques, ou bien des réseaux de composants pour les circuits analogiques). Les outils de conception existants sont destinés à traiter des systèmes homogènes en utilisant un seul formalisme à la fois. Dans l'état actuel, l'industrie se bat avec des problèmes d'intégration à chaque étape de la conception, à savoir la spécification, la simulation, la validation et le déploiement. L'absence d'une approche qui comprend les spécifications des interfaces inter-domaines est souvent la cause des problèmes d'intégration de différentes parties d'un système hétérogène. Cette thèse propose une approche pour faire face à l'hétérogénéité en utilisant SysML comme outil fédérateur. Notre proposition repose sur la définition d'une sémantique explicite pour les diagrammes SysML ainsi que des éléments d'adaptation sémantiques capables d'enlever les ambiguïtés dans les interfaces multi-domaines. Pour démontrer l'efficacité de ce concept, un ensemble d'outils basés sur l'ingénierie dirigé par les modèles a été construit pour générer du code exécutable automatiquement à partir des spécifications. / In the era of highly integrated electronics systems, engineers face the challenge of designing and testing multi-faceted systems with single-domain tools. This is difficult and error-prone. These so called heterogeneous systems have their operation and specifications expressed by several formalisms, each one particular to specific domains or engineering fields (software, digital hardware, analog, etc.). Existing design tools are meant to deal with homogeneous designs using one formalism at a time. In the current state, industry is forced to battle with integration issues at every design step, i.e. specification, simulation, validation and deployment. Common divide-to-conquer approaches do not include cross-domain interface specification from the beginning of the project. This lack is often the cause of issues and rework while trying to connect parts of the system that were not designed with the same formalism. This thesis proposes an approach to deal with heterogeneity by embracing it from the beginning of the project using SysML as the unifying tool. Our proposal hinges on the assignment of well-defined semantics to SysML diagrams, together with semantic adaptation elements. To demonstrate the effectiveness of this concept, a toolchain is built and used to generate systems simulation executable code automatically from SysML specifications for different target languages using model driven engineering techniques.

Les travaux de thèse présentés dans ce manuscrit portent sur le développement d'une nouvelle architecture de transmission spécifiquement dédiée aux réseaux de capteurs sans fils et adaptée aux caractéristiques particulières de ceux-ci. L'approche, basée sur les techniques de radio impulsionnelle pour la transmission à large bande, est développée selon deux aspects de recherche principaux: fonctionnel et matériel. L'aspect fonctionnel vise à définir les caractéristiques du signal transmis ainsi que les algorithmes de traitement (modulation et démodulation) associés. Plus largement, il s'agit de définir l'architecture fonctionnelle de la chaîne de transmission, selon deux modes différents d'exploitation: mono-utilisateur et multi-utilisateurs. L'approche proposée pour transmettre des signaux impulsionnels, est basé sur l'emploi de la transformée discrète en paquets d'ondelettes (DWPT) au niveau du récepteur et de la transformée inverse au niveau de l'émetteur (IDWPT). La nature orthogonale des ondelettes permet de réaliser, sans nécessiter une couche MAC complexe, des communications multi-utilisateurs, simultanées ou non, sur un canal large bande, grâce à la forte discrimination entre les impulsions transmises. Le deuxième aspect porte sur le développement des architectures matérielles permettant l'implantation des algorithmes de traitement développés dans la partie fonctionnelle. La recherche de performances élevées (ratio élevé entre vitesse de traitement et coût matériel) et flexibilité (configurabilité, extensibilité), est particulièrement important dans les fonctionnalités liées aux transformées discrètes en paquets d'ondelettes qui constituent le cœur critique de la chaîne de transmission. Des techniques de parallélisation massive et générique sont développées et mises en œuvre, permettant d'atteindre les niveaux de performances et de flexibilité requis. La validation a été réalisée à l'aide respectivement de modélisations et imulations sous Simulink/Matlab (de MathWorks) pour les aspects fonctionnels et de modélisations VHDL (au niveau RTL [Register Transfer Level]) et d'implantations sur FPGA pour les aspects matériels / The thesis work presented in this manuscript focuses on the development of a new transmission architecture specifically dedicated to wireless sensor networks and adapted to the particular characteristics of the later. The approach, based on impulse radio techniques for wideband transmission, is developed according to two main research aspects: functional and hardware. The functional aspect aims at defining the characteristics of the transmitted signal as well as the associated processing algorithms (modulation and demodulation). More broadly, it comes to define the functional architecture of the transmission chain, according to two different operating modes: mono- and multi-user. The proposed approach for transmitting pulse signals is based on the use of the discrete wavelet packet transform (DWPT) at the receiver and the inverse transform (IDWPT) at the transmitter. The orthogonal nature of the wavelets makes it possible, without needing a complex MAC layer, to make multi-user communications, either simultaneous or not, over a wideband channel, thanks to the strong discrimination between the transmitted pulses. The second aspect relates to the development of hardware architectures allowing the implementation of the processing algorithms developed in the functional part. The search for high performance (high ratio between processing speed and hardware cost) and flexibility (configurability, extensibility) is particularly important in the functionality related to the discrete wavelet packet transform which constitutes the critical core of the transmission chain. Massive and generic parallelization techniques are developed and implemented to achieve the required levels of performance and flexibility. Validation was carried out using respectively Simulink/Matlab (MathWorks) modeling and simulation for the functional aspects, and VHDL modeling (at the Register Transfer Level -- RTL) and FPGA implementations for the hardware aspects

In dieser Arbeit wird die Möglichkeit der Unterstützung des Hardwareentwurfs mit VHDL durch ein Hardwarebetriebssystem untersucht. Durch die Wiederverwendung von Betriebssystemmodulen sollen die Entwicklungszeit verkürzt, die Nachnutzbarkeit von Entwürfen verbessert und die Zuverlässigkeit erhöht werden. Um ein Betriebssystemkonzept umzusetzen, müssen spezielle Anforderungen an die Programmiersprache gestellt werden. Diese werden von VHDL nicht erfüllt. Daher wird ein Strukturcompiler vorgestellt, der unter Beibehaltung der Syntax der Sprache VHDL den zusätzlichen Anforderungen gerecht wird. Der Strukturcompiler verbindet das Anwendungsprogramm mit den Betriebssystemmodulen und erzeugt daraus ein VHDL-Programm, das mit den typischen FPGA-Entwicklungswerkzeugen simuliert oder synthetisiert werden kann. Bei der Entwicklung des Betriebssystems für konfigurierbare Hardware hat sich herausgestellt, dass sich dieses nur eingebettet in ein Gesamtkonzept für den Entwurf von heterogene Systeme sinnvoll anwenden lässt. Deshalb wird in dieser Arbeit eine Methode für die Entwicklung von heterogenen Systemen auf Basis eines Signalflussgraphen diskutiert. Angewendet wurde das Betriebssystemkonzept auf verschiedenen FPGA-Karten, sowohl käuflich erworbene als auch Eigenentwicklungen. Das für diese Karten erstellte Betriebssystem umfasst dabei Module zur Kommunikation zwischen FPGA und PC sowie zur Anbindung verschiedener externer Peripheriegeräte, wie z.B. Speicher. Es wurde ebenfalls untersucht wie Prozessoren als Bestandteil der konfigurierbaren Hardware in das Betriebssystemkonzept integriert werden können. Im Rahmen dieser Arbeit wurden auch viele Beispielanwendungen untersucht. Diese wurden einerseits zum Testen des Strukturcompilers und der Betriebssystemmodule benutzt. Andererseits fand das Betriebssystemkonzept für konfigurierbare Hardware auch Anwendung in verschiedenen Projekten. / This work investigates the possibility of describing a hardware design independent of special hardware. This is realized with the concept of an operating system. The re-use of operating system modules reduces the time of development and also increases the reliability. Additionally, the change of a development platform has no influence on the application algorithm anymore. In order to apply the concept of an operating system special constraints have to be fulfilled by the hardware description language, which is not supported by VHDL. For that reason a structure compiler has been developed. The structure compiler connects the application program with the operating system modules and produces a VHDL program, which can be used to simulate or to program the FPGA with the typical VHDL development tools. In the progress of developing the operating system concept for reconfigurable hardware it was realized that such a concept can only be used in connection with a design methodology for heterogeneous systems. In this work a design methodology based on a declarative language represented as signal flow graph is discussed. The operating system concept for reconfigurable hardware was tested on different FPGA boards. For these cards an operating system was developed. The operating system contains modules for the communication with the PC over different interfaces as well as modules for accessing different exterior peripheries, i.e. memory. Additionally, the integration of processors as part of the configurable hardware within the operating system concept was investigated. For the verification of the structure compiler and the operating system modules some examples have been developed. The operating system concept for configurable hardware was also applied in different projects.

Depuis les premiers ordinateurs on est en quête de machines plus rapides, plus puissantes, plus performantes. Après avoir épuisé le filon de l’augmentation de la fréquence, les constructeurs se sont tournés vers les multi-cœurs. Le modèle de calcul actuel repose sur les threads de l'OS qu’on exploite à travers différents langages à constructions parallèles. Cependant, la programmation multithread reste un art délicat car le calcul parallèle découpé en threads souffre d’un grand défaut : il est non déterministe.Pourtant, on peut faire du calcul parallèle déterministe, à condition de remplacer le modèle des threads par un modèle s’appuyant sur l’ordre partiel des dépendances. Dans cette thèse, nous proposons un modèle alternatif d’architecture qui exploite le parallélisme d’instructions (ILP) présent dans les programmes. Nous proposons de nombreuses techniques pour s’affranchir de la plupart des dépendances architecturales et obtenir ainsi un ILP qui croît avec la taille de l’exécution. L’ILP qu’on atteint de cette façon est suffisant pour permettre d’alimenter plusieurs milliers de cœurs. Les dépendances architecturales sérialisantes ayant été supprimées, l’ILP peut être bien mieux exploité que dans les architectures actuelles. Un code VHDL au niveau RTL de l’architecture a été développé pour en mesurer les avantages. Les résultats de synthèse d’un processeur allant de 2 à 64 cœurs montrent que la vitesse du matériel que nous proposons reste constante et que sa surface varie linéairement avec le nombre de cœurs. Cela prouve que le modèle d’interconnexion proposé est extensible. / The pursuit for faster and more powerful machines started from the first computers. After exhausting the increase of the frequency, the manufacturers have turned to another solution and started to introduce multiples cores on a chip. The computational model is today based on the OS threads exploited through different languages offering parallel constructions. However, parallel programming remains an art because the thread management by the operating system is not deterministic.Nonetheless, it is possible to compute in a parallel deterministic way if we replace the thread model by a model built on the partial order of dependencies. In this thesis, we present an alternative architectural model exploiting the Instruction Level Parallelism (ILP) naturally present in applications. We propose many techniques to remove most of the architectural dependencies which leads to an ILP increasing with the execution length. The ILP which is reached this way is enough to allow feeding thousands of cores. Eliminating the architecutral dependencies serializing the run allows to exploit the ILP better than in actual microarchitectures. A VHDL code at the RTL level has been implemented to mesure the benefits of our design. The results of the synthesis of a processeur ranging from 2 to 64 cores are reported. They show that the speed of the proposed material keeps constant and the surface grows linearly with the number of cores : our interconnect solution is scalable.

À l'ère de systèmes électroniques intégrés, les ingénieurs font face au défi de concevoir et de tester des systèmes hétérogènes contenant des parties analogiques, numériques, mécaniques et même du logiciel embarqué. Cela reste très difficile car il n'y a pas d'outil unifiant ces différents domaines de l’ingénierie. Ces systèmes, dits hétérogènes, ont leur comportement exprimées et spécifiés par plusieurs formalismes, chacun particulier à son domaine d'expertise (diagramme de machines à état pour les circuits de contrôle numérique, équations différentielles pour les modèles mécaniques, ou bien des réseaux de composants pour les circuits analogiques). Les outils de conception existants sont destinés à traiter des systèmes homogènes en utilisant un seul formalisme à la fois. Dans l'état actuel, l'industrie se bat avec des problèmes d'intégration à chaque étape de la conception, à savoir la spécification, la simulation, la validation et le déploiement. L'absence d'une approche qui comprend les spécifications des interfaces inter-domaines est souvent la cause des problèmes d'intégration de différentes parties d'un système hétérogène. Cette thèse propose une approche pour faire face à l'hétérogénéité en utilisant SysML comme outil fédérateur. Notre proposition repose sur la définition d'une sémantique explicite pour les diagrammes SysML ainsi que des éléments d'adaptation sémantiques capables d'enlever les ambiguïtés dans les interfaces multi-domaines. Pour démontrer l'efficacité de ce concept, un ensemble d'outils basés sur l'ingénierie dirigé par les modèles a été construit pour générer du code exécutable automatiquement à partir des spécifications. / In the era of highly integrated electronics systems, engineers face the challenge of designing and testing multi-faceted systems with single-domain tools. This is difficult and error-prone. These so called heterogeneous systems have their operation and specifications expressed by several formalisms, each one particular to specific domains or engineering fields (software, digital hardware, analog, etc.). Existing design tools are meant to deal with homogeneous designs using one formalism at a time. In the current state, industry is forced to battle with integration issues at every design step, i.e. specification, simulation, validation and deployment. Common divide-to-conquer approaches do not include cross-domain interface specification from the beginning of the project. This lack is often the cause of issues and rework while trying to connect parts of the system that were not designed with the same formalism. This thesis proposes an approach to deal with heterogeneity by embracing it from the beginning of the project using SysML as the unifying tool. Our proposal hinges on the assignment of well-defined semantics to SysML diagrams, together with semantic adaptation elements. To demonstrate the effectiveness of this concept, a toolchain is built and used to generate systems simulation executable code automatically from SysML specifications for different target languages using model driven engineering techniques.

This thesis is composed of three main parts / displaying an analog composite video input by via converting to digital VGA format, license plate localization on a video image and image enhancement on FPGA. Analog composite video input, either PAL or NTSC is decoded on a video decoder board / then on FPGA, video data is converted from 4:2:2 YCbCr format to RGB. To display RGB data on the screen, line doubling de-interlacing algorithm is used since it is efficient considering computational complexity and timing. When taking timing efficiency into account, image enhancement is applied only to beneficial part of the image. In this thesis work, beneficial part of the image is considered as numbered plates. Before image enhancement process, the location of the plate on the image must be found. In order to find the location of plate, a successful method, edge finding is used. It is based on the idea that the plate is found on the rows, where the brightness variation is largest. Because of its fast execution, band-pass filtering with finite response (FIR) is used for highlighting the high contrast areas. Image enhancement with rank order filter method is chosen to remove the noise on the image. Median filter, a rank order filter, is designed and simulated. To improve image quality while reducing the process time, the filter is applied only to the part of the image where the plate is. Design and simulation is done using hardware design language VHDL. Implementations of the chosen approaches are done on MATLAB and Xilinx Virtex-2 Pro FPGA. Improvement of the implementation considering speed and area is evaluated.

Šiame darbe tiriama, kaip kinta procesorinių komponentų (ALU įrenginio, duomenų registro, instrukcijų registro bei programos skaitiklio registro) techniniai parametrai keičiant procesoriaus apdorojamos informacijos dydį bitais. Su Synopsys programine įranga buvo susintezuoti komponentų VHDL programavimo kalba parašyti aprašai, taip gaunant apytikrius procesorinių komponentų techninius parametrus (kristalo plotas, schemai realizuoti reikalingas elementų kiekis, schemos vidinis galingumas). Šiam tikslui buvo susintezuoti procesoriniai komponentai, kurie apdorja 8, 16, 32 ir 64 bitų ilgio duomenis. Tai dažniausiai sutinkami duomenų ilgiai, su kuriais tenka susidurti dabartiniams procesoriams. Iš gautų sintezės rezultatų padaryta išvada, kad keičiant apdorojamų duomenų ilgį bitais galima preliminariai numatyti susintezuotos schemos kristalo plotą, schemai realizuoti reikalingą loginių elementų kiekį, vidinį schemos galingumą. Buvo nustatyta, kad didėjant apdorojamos informacijos kiekiui, padidėja įrenginių, kurie galėtų apdoroti šią informaciją, kristalo plotas, jiems realizuoti reikalingas loginių elementų kiekis bei vidinis galingumas. / This work examines how the change of processed data length influence the technical parameters of processor’s components such as arithmetic logic unit (ALU), data registers, instruction registers and program counter registers. It was done by using Synopsis software which enabled the synthesis of the needed components. The synthesis results showed information about occupied area, the number of cells and the internal voltage of the synthesised scheme. There were chosen the most common length of processed data (8, 16, 32 and 64 bit). The results of synthesis showed, that it is possible to predict the results of synthesis by changing the length of the processed data. The longer word of information must be processed by components, the larger area is needed for implementation of the processor components, more logical element are needed to implement the components and the greater internal voltage of the scheme will be.

A crescente demanda da indústria exige a produção de dispositivos embarcados em menos tempo e com mais funcionalidades diferentes. Isso implica diretamente no processo de desenvolvimento destes produtos requerendo novas técnicas para absorver a complexidade crescente dos projetos e para acelerar suas etapas de desenvolvimento. A linguagem UML vem sendo utilizada para absorver a complexidade do projeto de sistemas embarcados através de sua representação gráfica que torna o processo mais simples e intuitivo. Para acelerar o desenvolvimento surgiram processos que permitem, diretamente a partir modelos UML, a geração de código para linguagens de descrição de software embarcado (C, C++, Java) e para linguagens tradicionais de descrição de hardware (VHDL, Verilog). Diversos trabalhos e ferramentas comerciais foram desenvolvidos para automatizar o processo de geração de código convencional a partir de modelos UML (software). No entanto, pela complexidade da transformação existem apenas poucos trabalhos e nenhuma ferramenta comercial direcionado à geração de HDL a partir de UML, tornando este processo ainda pouco difundido. Nossa proposta é focada na geração de descrições de hardware na linguagem VHDL a partir de modelos UML de sistemas tempo-real embarcados (STRE), surgindo como alternativa ao processo de desenvolvimento de hardware. Apresenta uma metodologia completa para geração automática de código VHDL, permitindo que o comportamento descrito para o sistema modelado seja testado e validado antes de ser desenvolvido, acelerando o processo de produção de hardware e diminuindo as chances de erros de projeto. É proposto como um processo de engenharia dirigido por modelos (MDE) que cobre desde as fases de análise de requisitos e modelagem UML, até a geração de código fonte na linguagem VHDL, onde o foco é gerar na forma de descrições de hardware, todas aquelas funções lógicas de um sistema embarcado que normalmente são desenvolvidas em software. Para atingir este objetivo, foi desenvolvido neste trabalho um conjunto de regras de mapeamento que estende a funcionalidade da ferramenta GenERTiCA, utilizada como suporte ao processo. Adicionalmente, foram pesquisados e desenvolvidos conceitos que serviram como base para o desenvolvimento de regras utilizadas pela ferramenta suporte para guiar o processo de mapeamento entre as linguagens. Os conceitos e as regras propostas foram validados por meio de um estudo de caso, cujos resultados obtidos estão demonstrados nesta dissertação. / The growing market demand requires the production of embedded devices in less time and with more different features. This directly implies on the development process of these products requiring new techniques to absorb the growing complexity of projects and to accelerate their development stages. UML has been used to handle the embedded systems design complexity through its graphical representation that makes the process simpler and more intuitive. To speed up the development cycle, it has emerged some processes that permit code generating directly from UML models to embedded software description languages (C, C++, Java), and traditional hardware description languages (VHDL, Verilog). Several researches and commercial tools have been developed to automate the code generation process from UML models to conventional languages (software). However, due to the transformation complexity there are only few studies and no commercial tool addressed to HDL generation from UML models, making this process almost unknown. Our proposal is focused on generating hardware descriptions as VHDL code from UML models of real-time embedded systems (RTES), emerging as an alternative to the hardware development. It presents a complete methodology to the VHDL code generation, allowing the behavior described to the modeled system to be tested and validated before being implemented, accelerating the hardware production and decreasing the chances of design errors. It is proposed as a model-driven engineering (MDE) process that covers the phases of requirements analysis, UML modeling, models transformations, and the source code generating process to the VHDL language, where the focus is to generate as hardware descriptions all the logic functions of an embedded system which are usually developed as software. To achieve this goal, this work was developed a set of mapping rules which extends the functionality of the tool GenERTiCA, used to support the process. Additionally, it was researched and developed concepts that were the basis for the development of rules used by the tool support to guide the mapping process between languages. The concepts and proposed rules have been validated through a case study, whose results are shown in this dissertation.