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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
21

MODELING AND SIMULATION OF AN FM RECEIVER USING VHDL-AMS

REVANURU, MURTHY N. 11 October 2001 (has links)
No description available.
22

Σχεδίαση του αλγόριθμου quadtree decomposition με γλώσσα περιγραφής VHDL για grayscale τετραγωνική εικόνα

Κουκούλα, Βαλσαμίνα 14 October 2013 (has links)
Η απεικόνιση και συμπίεση χωρικών δεδομένων έχει γίνει ένα θέμα έμφασης και προσοχής για τον τομέα των computer graphics και για εφαρμογές επεξεργασίας εικόνας. Τα quadtrees, σαν μία από τις ιεραρχικές δομές δεδομένων, βασιζόμενα στην αρχή του επαναλαμβανόμενου διαχωρισμού του χώρου, προσφέρουν πάντα μία συμπαγή και αποτελεσματική αντιπροσώπευση μίας εικόνας. Ο σκοπός αυτής της εργασίας είναι η ανάλυση του αλγορίθμου quadtree, και η σχεδίαση του αλγορίθμου με γλώσσα VHDL. Αναλύεται η μηχανή καταστάσεων και το datapath του υπό ανάπτυξη κυκλώματος. Επίσης παρουσιάζονται κυματομορφές των σημάτων της κάθε κατάστασης από την προσομοίωση που έγινε στο Modelsim. Για την επιβεβαίωση της λειτουργίας του κυκλώματος, έγινε σύνθεση του κυκλώματος με τη βοήθεια του προγράμματος ISE της Xilinx. Όσον αφορά την υλοποίηση, χρησιμοποιήθηκε το board της Xilinx Virtex-5 FPGA ML 507 και εξομοίωση λειτουργίας για εικόνα μεγέθους 64x64. Στο Παράρτημα παρουσιάζονται ο κώδικας Matlab της συνάρτησης qtdecomp που χρησιμοποιήθηκε για την κατανόηση του αλγόριθμου quadtree και καθώς και ο κώδικας Matlab που δημιουργήθηκε για να επαληθεύσει τα αποτελέσματα της προσομοίωσης με Modelsim. / Compression of spatial data has become a matter of emphasis and attention in the field of computer graphics and image processing applications. The quadtrees, as one of the hierarchical data structures, applies the principle of repetitive decomposition of space and offers a compact and efficient representation of an image. The purpose of this paper is to analyze the algorithm quadtree, and to design the algorithm with the language VHDL. In this paper the state machine is analyzed as well as the datapath of the circuit. Furthermore the waveforms of the control signals for each state are presented from the simulation done in the Modelsim environment. A confirmation of the operation of the circuit took also place.The circuit was composed with the help of the ISE of Xilinx. Regarding the implementation, the board of Xilinx Virtex-5 FPGA ML 507 is used and the emulation is done for a picture sized 64x64. The Annex outlines code of the MATLAB function qtdecomp used for understanding the quadtree algorithm and the Matlab code created to verify the simulation results of Modelsim.
23

GSM LPC komponento realizavimas ir tyrimas / GSM LPC component implementation and testing

Chaladauskas, Mindaugas 13 August 2010 (has links)
Kiekvienas, kuris kuria aparatūrinę įrangą, nori, tai atlikti kiek įmanoma greičiau ir už kuo mažesnius kaštus. Gaminys turi greitai patekti į rinką, nes egzistuojanti konkurencija yra labai didelė. Tai galima padaryti naudojant specialią programinę įrangą, vadinamus aukšto lygio sintezės įrankius. HLS įrankiai automatiškai generuoja HDL RTL aprašą bei padeda projektuotojams turėti visas galimas projekto architektūras. HLS įrankiai naudoja algoritminį C aprašą kaip įvesties duomenis. Čia atsiranda galimybė PĮ inžinieriams taip pat projektuoti aparatūrinę įrangą. Nors atrodo, jog HLS technologija yra labai gera, bet šie įrankiai šiandien plačiai nėra naudojami. Turi būti surasti problemu sprendimai. Šioms problemoms spręsti atliekamas eksperimentas. GSM LPC algoritmas rankiniu būdu perrašomas iš C kalbos aprašo į VHDL RTL. Eksperimentas paaiškina aukšto lygio sintezės problemas. Norint, kad HLS įrankiai būtų plačiai naudojami, aukšto abstrakcijos lygio C/C++ aprašas turi būti rašomas su atitinkamais apribojimais. Neturi būti naudajami rodyklės tipo kintamieji, rodyklės tipo kintamųjų aritmetikos, rekursijos, sudėtingų operacijų, dinaminio atminties rezervavimo. Projektuotojai turi mąstyti taip kaip aparatūrinė įranga. / Everyone who develops hardware wants to do this as fast as possible and for low costs. Time to the market must be shortened because the competition is very substantial. This can be done by using special development software called high level synthesis tools. HLS tools automatically generate HDL RTL code and helps developers to get all possible architectures of project. HLS tools use an algorithmic C code as input information. There is the possibility for software engineers to develop hardware too. It seems that HLS is very good technology, but HLS tools are not widely used today. It must be found the reasons of this problem and opportunities how this problem can be solved. An experiment is made by solving this problem. A GSM LPC algorithm is written by hand from C description to VHDL RTL. This experiment explains problems of high level synthesis. With the purpose HLS tools to use widely, high level of abstraction (C/C++) code must be written with restrictions. There must be no pointer variables and pointer arithmetic, no recursion, no difficult operations, no dynamic memory allocation. Engineers have to think like hardware.
24

Integration of VHDL simulation and test verification into a Process Model Graph design environment /

Dailey, David M., January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 116-117). Also available via the Internet.
25

Design and Implementation of an Universal Lattice Decoder on FPGA

Kura, Swapna 20 May 2005 (has links)
In wireless communication, MIMO (multiple input multiple output) is one of the promising technologies which improves the range and performance of transmission without increasing the bandwidth, while providing high rates. High speed hardware MIMO decoders are one of the keys to apply this technology in applications. In order to support the high data rates, the underlying hardware must have significant processing capabilities. FPGA improves the speed of signal processing using parallelism and reconfigurability advantages. The objective of this thesis is to develop an efficient hardware architectural model for the universal lattice decoder and prototype it on FPGA. The original algorithm is modified to ensure the high data rate via taking the advantage of FPGA features. The simulation results of software, hardware are verified and the BER performance of both the algorithms is estimated. The system prototype of the decoder with 4-transmit and 4-receive antennas using a 4-PAM (Pulse amplitude modulation) supports 6.32 Mbit/s data rate for parallelpipeline implementation on FPGA platform, which is about two orders of magnitude faster than its DSP implementation.
26

Sound Level Measurement System

Johansson, Tore January 2006 (has links)
<p>The purpose of this master thesis work is to design a device that measures the loudness of sound for different frequencies. This device is divided in three parts; a microphone that captures the sound, one A/D converter that samples the sound and one FPGA which analyse the data using an FFT algorithm.</p><p>LEDs connected to the FPGA are used to indicate different output levels. A db(A) filter is applied that weights each frequency, before the different outputlevels are measured for each frequency. </p><p>This system is supposed to be a subsystem to a larger system that is developed in a company. However, because of the risk that competitors might be able to guess the next product move of the company, the company is anonymous in this report. All the components used are paid for by the company and in return the company gets an idea of the complexity of the system and a basis for future design decisions.</p>
27

Sound Level Measurement System

Johansson, Tore January 2006 (has links)
The purpose of this master thesis work is to design a device that measures the loudness of sound for different frequencies. This device is divided in three parts; a microphone that captures the sound, one A/D converter that samples the sound and one FPGA which analyse the data using an FFT algorithm. LEDs connected to the FPGA are used to indicate different output levels. A db(A) filter is applied that weights each frequency, before the different outputlevels are measured for each frequency. This system is supposed to be a subsystem to a larger system that is developed in a company. However, because of the risk that competitors might be able to guess the next product move of the company, the company is anonymous in this report. All the components used are paid for by the company and in return the company gets an idea of the complexity of the system and a basis for future design decisions.
28

A framework for synthesis from VHDL /

Shah, Sandeep R., January 1991 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1991. / Vita. Abstract. Includes bibliographical references (leaves 91-94). Also available via the Internet.
29

Behavior modeling of RF systems with VHDL /

Sama, Anil, January 1991 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1991. / Vita. Abstract. Includes bibliographical references (leaf 107). Also available via the Internet.
30

Rapid development of VHDL behavioral models /

Wright, Philip A., January 1992 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 56-57). Also available via the Internet.

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