The purpose of this thesis was to implement a serial communication port model for a digital signal processor. It is a behavioral model, developed using VHDL, that is instruction comparisable to the Motorola digital signal processor DSP 56002. It supports five different data transfer modes and provides a programmable baud rate generator. This report starts out by giving a description of the external port, port C, the pin control logic and general purpose functionality. Then a more detailed description of the three pin dedicated serial communication interface is presented, the different operating modes and the baud rate generator are described.

The fast growth of wireless local area networks today has opened up a whole new market for wireless solutions. Released in 1999, the IEEE 802.11a is a standard for high-speed wireless data transfer that much of modern Wireless Local Area Network technology is based on. This project has been about implementing the transmitter part of the 802.11a physical layer in VHDL to run on the Altera Stratix II FPGA. Special consideration was taken to divide the system into parts based on sample rate. This report contains a brief introduction to Orthogonal Frequency Division Multiplexing and to the IEEE 802.11a physical layer as well as a description of the implemented system.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003. / Thesis advisor(s): Douglas J. Fouts, Phillip E. Pace. Includes bibliographical references (p. 143-144). Also available online.

Η παρούσα εργασία περιλαµβάνει την µοντελοποίηση του block cipher αλγόριθµου κρυπτογραφίας Anubis σε γλώσσα VHDL, και την επαλήθευση λειτουργίας του επί πλακέτας FPGA. Ο αλγόριθµος Anubis ήταν µεταξύ των συµµετεχόντων αλγορίθµων στον ευρωπαϊκό διαγωνισµό NESSIE. Στο Κεφάλαιο 1 γίνεται µία σύντοµη παρουσίαση των βασικών όρων και εννοιών της κρυπτογραφίας, και παρουσιάζεται ο τρόπος λειτουργίας των σύγχρονων αλγορίθµων κρυπτογραφίας. Στο Κεφάλαιο 2 παρουσιάζεται ο αλγόριθµος Anubis και οι µαθηµατικές συνιστώσες των δύο λειτουργιών που τον απαρτίζουν: της λειτουργίας υπολογισµού της key sequence και της καθαυτό λειτουργίας κρυπτογράφησης/αποκρυπτογράφησης δεδοµένων. Στο Κεφάλαιο 3 παρουσιάζονται εν συντοµία τα υλικά και τα προγράµµατα που χρησιµοποιήθηκαν για την ανάπτυξη της παρούσας εργασίας. Στο Κεφάλαιο 4 αναλύεται η υλοποίηση του αλγορίθµου, µε την περιγραφή των δοµικών του στοιχείων, του υποσυστήµατος ελέγχου και χρονισµού, µε ιδιαίτερη έµφαση σε σηµεία όπου έγιναν ιδιαίτερες σχεδιαστικές επιλογές. Στο Κεφάλαιο 5 παρουσιάζεται η προσαρµογή και εφαρµογή του VHDL µοντέλου pου αναπτύχθηκε σε πλακέτα FPGA της οικογένειας Virtex-5, καθώς και οι µετρήσεις που ελήφθησαν σε αυτή. Το σύστηµα που σχεδιάστηκε αρχικά αφορά τον πλήρη αλγόριθµο, για όλο το δυνατό εύρος κλειδιών από 128 έως 320 bits και για είσοδο plaintext/ciphertext των 128 bits. Δεν περιλαµβάνονται στη σχεδίαση περιφερειακά συστήµατα όπως γεννήτρια κλειδιών ή µνήµες και µονάδες εισόδου/εξόδου. Έγινε µερική µόνο υλοποίηση των λειτουργιών αυτών µέσω ενός προγράµµατος wrapper ώστε να δοκιµαστεί η λειτουργία του επί του FPGA. Λόγω περιορισµών του FPGA που διετίθετο, η υλοποίηση που δοκιµάστηκε αφορούσε έκδοση των 256 bits. Σε αντίθεση µε άλλους, πιο διαδεδοµένους αλγόριθµους, ως τώρα δεν υπάρχει κάποια αντίστοιχη υλοποίηση για τον Anubis. Ως εκ τούτου συγκρίσεις για την απόδοσή του ως προς ταχύτητα ή κατανάλωση επιφανείας µπορούν να γίνουν µόνο µε τις software εκδοχές του και µε άλλους παρεµφερείς αλγόριθµους. / VHDL design and testing on FPGA of the Anubis block cipher.

Les codes correcteurs d'erreurs LDPC (Low Density Parity Check) font partie des codes en bloc permettant de s'approcher de quelques fractions de dB de la limite de Shannon. Ces remarquables performances associeés à leur relative simplicité de décodage rendent ces codes très attractifs pour les prochaines générations de systèmes de transmissions numériques. C'est notamment déjà le cas dans la norme de télédiffusion numérique par satellite (DVB-S2) qui utilise un code LDPC irrégulier pour la protection de la transmission des données descendantes. Dans cette thèse, nous nous sommes intéressés aux algorithmes de décodage des codes LDPC et à leur implantation matérielle. Nous avons tout d'abord proposé un algorithme sous-optimal de décodage (l'algorithme lambda-min) permettant de réduire de façon significative la complexité du décodeur sans perte de performances par rapport à l'algorithme de référence dit propagation de croyance (algorithme BP). Nous avons ensuite étudié et conçu une architecture générique de décodeur LDPC,que nous avons implantée sur une plateforme dédiée à base de circuits logiques programmables FPGA. Ce décodeur matériel permet avant tout d'accélérer les simulations d'un facteur supérieur à 500 par rapport à une simulation logicielle. De plus, par sa conception entièrement programmable, modulaire et générique, il possède de nombreuses fonctionnalités: Il peut ainsi être configuré pour une large classe de codes, et en conséquence permettre la recherche de codes efficaces

This project was carried out as thesis work during the last semester of my Master studies Electronics Design at the Mid Sweden University. Firstly, it considers a robust and exible implementation of ITU-G4 in hardware based on earlier work, and secondly, it covers review of related work and investigation in the weaknesses of two published designs. More specically, it is an investigation on the robustness of the previously developed VHDL implementation ofthe ITU-G4 algorithm. This includes designing of a debug interface to track the compression process inside the FPGA. The nal result, when comparing to earlier work and other published designs, the ITU-G4 compression performs without any glitches or crashes at certain patterns. The maximum frame rate the design can run at is 60fps at a frame size of 752x480 and clockrate of 33.3MHz. The design is tested with three sets of images: easy, medium and complexwhich are all successfully compressed. This includes imperfect images of bar-codes and Q-codes without the need of morphological preprocessing when comparing to the published design that needs preprocessing for medium and complex images to remove unexpected transitions.

For any practical implementation of chip design, there needs to be a hardware platform available for the purpose of prototyping and implementation of FPGA-based programs, whether they are written in VHDL or Verilog. Communication between the platform and a computer is a useful feature of many hardware solutions as it allows for the capability of regular data transmission between the two devices. Furthermore, the ability to communicate between the platform and a computer at high-speeds requires a specially constructed interface, one that can be modified by the designer at their choosing. There are a number of commercial packages which provide a hardware platform to perform this task, however there are drawbacks to many of the available options. Some may require special hardware to connect to a computer using proprietary connectors or boards, which increases the cost and reduces the flexibility of any solution. Other options may have limited access to the internal structure of the interface, limiting the ability of the developer to modify the interface to suit their needs. There may be an extra cost to provide the code to the interface, separate from the board, which can also tax design budgets. This dissertation provides a solution in the form of a Gigabit Ethernet connection with a custom IP/network layer written in VHDL to facilitate the connection. With an increasing number of IP-enabled devices available such as IPTV and set top boxes, the ability to link hardware using Ethernet is very useful and so the development of a lean and capable network layer was considered a suitable focus for the project. The overall goal has been to provide an interface which is cheap, open, robust and efficient, retaining the flexibility a developer might require to modify the code to their needs. After covering some basic background information about the project, the dissertation looks at the requirements of the board and interface, as well as the alternative interface solutions which were looked at before deciding on Gigabit Ethernet. The protocols used in Ethernet are then covered, with both an explanation of the structure of each and their relevance to the implementation. The Finite State Machines which control operation of the interface are covered in depth, with an explanation of their inter-connectivity to each other and how they fit in the data-flow between the computer and the board. Error correction and reliability is discussed, as well as any remaining components critical to the operation of the interface. Pipelining, the method of design which provides the speed required for Gigabit Ethernet, is covered along with the extra speed optimisation techniques used in the design such as RAM swinging buffers. Testing and synthesis are covered which ensure the design is as robust as possible, both in simulations and in real-world applications. The final design was implemented on a Xilinx Spartan 3 FPGA (XC3S5000-5FG900C) and capable of a maximum speed of 128.287 MHz, which is more than enough to satisfy the requirements of Gigabit Ethernet under a variety of network conditions. The interface code occupies 1,166 slices of logic on the FPGA (3% of the total amount of logic available), making it sufficiently compact to run large projects on the same chip. The core was tested on physical hardware and performed correctly at real line Gigabit speeds. Configuration of the computer along with the method of connecting to the board and transferring data is mentioned, with explanation of the code run on the computer to make this possible. Finally, the dissertation provides an example application through the use of JPEG2000 image compression/decompression.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1990. / Vita. Abstract. Includes bibliographical references (leaves 74-75). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 95-98). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 126-128). Also available via the Internet.